The efficiency demands of portable electronics, heat dissipation and pc-board real estate leave manufacturers with two ways to go. They can develop smaller packages toward the chip-scale ideal with the same die performance and thermal characteristics. Or they can put more silicon into the same size package (either with denser structures or by clearing out dead package space), improving power output and thermal performance. All the major MOSFET players are doing both, with the present emphasis on smaller packages.

The candle was most recently reignited by Fairchild Semiconductor (See May 1, page 135) with their Bottomless package, a wire-bond free affair that accommodates the bare solder-bumped die on the underside directly to the pc board. With that direct-conduction, the device junction-to-case thermal resistance parameter is below 1 degrees C per watt: a result that's said to be more than a twentyfold improvement in existing wire-bonded devices. The junction-to-ambient value, considered a more practical design parameter, is generally higher.

ChipFET, introduced by Vishay Siliconix in December, is based on the repositioning of device leads. The ChipFET technique brings leads to the bottom of the package, which increases available die area. Along similar lines, companies such as ON Semiconductor are adjusting their manufacturing to accommodate those new technologies. Indeed, efforts in the last reckoning are aimed at improving the percentage of active die utilization to given footprint. At Intersil, which recently developed Dense Trench, the goal is to improve the ratio by one and a half to four times within six to 12 months.

The packaging aspect will be adapted to higher powers within two years. Some concepts are still theoretical, though, so don't expect to see true packageless chips any time soon. Contamination, electrostatic discharge, making good connections, the expertise required and the cost keep that idea in a holding pattern.