It's no secret that interconnect design is a monster casting an ominous shadow over the future of high-density ICs. As real designs move warily closer to 0.1-micron processes, more problems are appearing. First it became clear that interconnect impedance was going to be a larger issue than gate delay on critical timing paths. Then we started hearing about more subtle issues: capacitive coupling between adjacent runs, inductive coupling between closely related runs and even antenna coupling between seemingly unrelated runs. We're trying to move signals at the frequencies the RF folks use for carriers.

One problem with these signal-integrity issues is that they can be pattern-dependent. They also require intense physical analysis to predict even if the exact shape of the metal stack is known, which it rarely can be. Maybe we will find adequate estimates, approximations and rules of thumb. The situation in the medium term does not look promising. We may have to accept, at some point, that on-chip interconnect is inherently a noisy communications channel and stop treating it as if it were a network of magic wormholes in the fabric of space.

Unfortunately, this runs counter to system-on-chip design trends. We have two interconnect camps. One wants to confine all random routing to the interior of rather small blocks and wire the blocks with standard on-chip buses. This approach is elegant and hierarchical for the RTL designer. But it looks like a catastrophe for the physical design folks.

Attempting to run large, fast buses with their dozens of long, narrow parallel tracks around on an 0.18-micron chip without creating disabling signal-integrity and clock-energy problems may be beyond the ability of current analysis tools.

So we have a second camp: Some designers say that even for block-level interconnect, point-to-point routing creates fewer problems.

The real solution may be ugly: Using buses just to manage routing complexity. But we may have to treat them as inherently unreliable channels, and use the error-correction strategies familiar to the communications and mass-storage industries. This would result in a hierarchical chip in which the most traffic-intensive blocks were linked by buses with error-correcting codes and hardware redundancy. This will make the interconnect latency between blocks much greater than the random wiring delay.

In an era of almost-free transistors, the overhead to build in error correction may be less than the inefficiency of design rules that could almost eliminate signal-integrity problems.