Some logic designers balk at adding more responsibilities to their already busy schedules. But any engineer who has missed a critical market window because of endless iterations between front- and back-end design understands the necessity. The old methodology of performing synthesis, then place and route, and postlayout optimization will not work for complex system-on-chip designs.

Customers involved in high-end designs tell me that achieving timing closure earlier in the design cycle is a top priority. Most engineers agree that a top-down, physical synthesis technology works best. Unlike a bottom-up approach, where timing-closure problems are solved after synthesis, a physical synthesis technology addresses timing closure early in the cycle, when RTL code can be altered and optimized most easily.

Physical synthesis tightly links logic synthesis and layout design. It updates the traditional design flow by bringing key physical functions into the front-end process. Logic decisions are based on accurate interconnect delay estimates derived from the placement, while the placement is driven by the timing constraints imposed by the logic configuration. Physical synthesis integrates both design phases into a single, simultaneous process. The designer can thus make fundamental design decisions (like which building blocks to use) with an awareness of the physical effects that determine basic circuit performance.

Physical synthesis is built on the fundamental premise that key decisions that take into account the chip's floor plan, placement, congestion analysis and physical libraries must be made during synthesis. Timing closure is achieved by simultaneously optimizing logic synthesis and placement while preserving design constraints, including area and power.

For physical synthesis to work best, however, logic designers must understand the floor plan well enough to use it to drive the synthesis process, because it reflects the architectural intent and drives the ultimate physical hierarchy of the design. The logic designer must also understand physical roadblocks, such as power strips, which can impede timing closure later in the design cycle.

Designers making the transition to physical synthesis, with the help of new EDA tools, reap several benefits. In addition to achieving timing closure, they are able to perform scan insertion and ordering, as well as power optimization, during the synthesis stage, all of which reduce costly iterations.

In time, physical synthesis will replace traditional synthesis for complex silicon designs. This prediction is based on more than 30 tapeouts that our customers have achieved by using physical synthesis technology.

Aart De Geus is Chairman and Chief Executive Officer of Synopsys Inc. (Mountain View, Calif.).