In the meantime, shrinking semiconductor process technologies have led to FPGAs with ASIC-like densities of a million gates or more. FPGAs offer low-risk prototypes without any mask charges or lengthy respin cycles to correct design errors. Since no custom foundry is involved, the design cycle is immediate. You just program and go. The FPGA is the product of choice when quick time-to-market is critical.

Still, FPGAs have drawbacks. Unit prices for high-density FPGAs are easily four to five times higher than those for comparable-density ASICs. FPGAs are notorious for high power consumption and relatively slow speeds.

Few companies ever alter the custom logic in their products in the field. Most companies using FPGAs for volume production pay to have them preprogrammed. Due to expensive silicon overhead and unit programming costs, FPGA programmability is usually an unnecessary production cost, not a benefit.

Why not combine the best of both worlds? The quick design cycles, zero NRE charges and no minimum orders of the FPGA design flow, with the low-cost and low-power characteristics of ASICs.

The optimum solution is to create convergence between the FPGA and ASIC design flows. This would start with an FPGA prototyping process in which the design benefits of reprogrammability are fully exploited. The next step would be a quick turnaround migration of this design to a less costly, special-purpose ASIC made to accept the FPGA design without re-engineering. To preserve timing relationships affected by place and route, design migration must be done directly from the customer's FPGA bit stream.

In order to effect an automated "hands-free" migration, the ASIC must be exactly compatible with the architecture of the FPGA prototype. If the logic elements of the FPGA used for prototyping include a lookup table and carry logic, then the target ASIC must have similar high-level logic structures.

ASIC manufacturing processes must also change so that the ASICs can be quickly delivered for system qualification. A single-layer custom configuration step would allow quick delivery from a ready inventory of "blank" wafers.

The technology to do this is available. FPGA design tools are advanced, and designers are familiar with HDL design flows. Some newer ASIC architectures mirror the high-level programmable logic of FPGAs. Both laser and mask processes are available that allow custom ASICs to be configured in a day.

For a few high-volume products, cost pressures cannot be offset by quick time-to-market, so conventional ASICs will never disappear. For most products, combining the best features of designing with FPGAs and manufacturing with ASICs while eliminating the problems of each is the best solution.

Don Knowlton is Vice President of Marketing at Clear Logic Inc. (Haddonfield, N.J.).