The biggest disappointment has been in performance. While some vendors have seriously overestimated the performance of their parts, most of the problem lies not in the actual performance but in describing NPU performance.

In the Wild West of the NPU market, there aren't any laws about performance descriptions. Vendors have generally classified their chips as "Gigabit Ethernet" or "OC-48" processors based on their line bandwidth and some basic throughput measurement in millions of packets per second (Mpps).

One problem is that some vendors haven't even taken the time to measure Mpps. I get suspicious when a vendor says its chip handles packets at OC-48 rates and then can't provide an Mpps number that corresponds to that speed. That's marketing, not engineering, talking.

The biggest problem, however, is that these Mpps numbers are invariably specified for basic Layer 3 routing, the simplest task an NPU can be asked to do. Performance inevitably decays when the chip executes more advanced functions, such as Multi-Protocol Label Switching.

These extra features are what NPUs are intended to handle. If all a router has to do is Layer 3 routing, you don't need a flexible device.

Because the NPU is programmable, it can do just about anything. But each new task requires more code for each packet. The more code per packet, the fewer packets that can be processed per second.

One cannot assume that a chip that delivers better Layer 3 routing performance will do better in a more complex environment. NPUs that rely heavily on programmable elements will degrade faster than chips with more hardwired coprocessors or those with pipelined designs. Some chips may have other shortcomings, such as limited memory bandwidth, that lead to performance bottlenecks.

Today's OC-48 NPUs are better suited to OC-12 designs when performing a real-world feature set, and most of next year's OC-192 chips will max out at OC-48.

NPUs still offer valuable flexibility needed in network equipment. But to reach high-end equipment, vendors will need to combine programmability and performance better than they have so far.

Linley Gwennap, Co-author of a Guide to Network Processors (www.linleygroup.com/npu), is Principal Analyst of the Linley Group.