United Business Media EE Times


Search

HOMEMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSSMost Popular contentTrusted Sources

 


A node too far
Print this article Email this article Reprints RSS Digital Edition

EE Times


Ron WilsonMighty Sony had to admit that the well-publicized shortage of chips for the Playstation 2 rollout was due to a porting problem. In moving one of the two huge system-level devices from one process to another, something broke and yields suffered, leading to a shortage.

The story is not unique, except for the high public profile of the company and the product. But it does raise an old question: When is it really time to move on to a new process?

Received wisdom from Moore's Law is that smaller is inherently better. Obviously, device density should increase with declining feature size. Less obviously — and the relationship is more complex than is usually suggested — stage delays can also decrease as features get smaller. Then again, they may not. A given design ought to fit on a smaller die in a more advanced process, but that too is not automatic.

The delay question is complicated by many issues. Yes, average interconnect lengths and parasitic capacitances should decrease. But drive levels may also decrease. Noise margins may shrink, and one of the costs of greater noise can be longer delays. Add in a few other effects, such as the need to compensate for uncertainties in clock skews, and it's not obvious that moving from 0.18 to 0.13 microns, for example, is an automatic win for performance.

On the density side, there is no improvement in die area for a pad-limited design unless there is a substantial improvement in pad density. But even for logi-limited designs, restrictive design rules and additional circuitry for power management, regulators for additional supply voltages and a host of other things can eat away at area savings.

Hovering over the whole question of migrating to a bleeding-edge process is the issue of risk. Processes themselves may not be as mature as tool developers would like. Tools may not exist to deal with some of the new process's unique design problems.

All those considerations make the decision to leap to a finer geometry less than obvious. Certainly, there will be added design costs, maybe large ones. Unless volumes are such that you can get by with a multiproject mask set, mask charges will be huge. Nothing else is assured.

The larger issue here is the blind pursuit of Moore's Law. Today our foundry and equipment industry investments are based on the assumption that the next process node is inevitable, good and desired. In reality, that assumption may only be true for a declining minority of very special projects — projects with such risk that taken together, they may one day fail to justify the investment.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


  Free Subscription to EE Times
First Name Last Name
Company Name Title
Email address
  Click here for your Free Subscription to EETimes Europe
 
CAREER CENTER
Looking for a new job?
SEARCH JOBS
SPONSOR

RECENT JOB POSTINGS
CAREER NEWS
SRC Expands R&D Centers
The Semiconductor Research Corp has added a new center to its university R&D efforts.

For more great jobs, career related news, features and services, please visit EETimes' Career Center.


All White Papers »   

 
Education and
Learning


Learn Now:












Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
Network Websites
International
Network Features




All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC All rights reserved.
Privacy Statement | Terms of Service | About