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Processes in the spotlight
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Linley GwennapRecent announcements from Intel and IBM highlight the escalating stakes in IC process development. At the International Electron Devices Meeting this week, Intel disclosed the world's fastest transistor, while IBM unveiled the world's most advanced production-ready IC process.

Intel's announcement was a pure research event. The company's scientists have built a single transistor with a switching time of less than 2 picoseconds. Perhaps most impressive, the transistor's gate oxide is only three atoms thick. This transistor will be used in Intel's 0.07-micron process, three generations beyond today's 0.18-micron process. Scheduled to enter production in 2005, the 0.07-micron process should push Pentium 4 speeds to 10 GHz.

This announcement shows that Moore's Law is on track for at least five more years. Significant advances must still be made to put the 0.07-micron process into production, but the key challenges have been met.

Beyond 2005, however, things still look dicey. Clearly, gate oxides are not going to get much thinner. High-k oxides could extend Moore's Law for another couple of generations, but 2010 could be the end for silicon.

In the meantime, the race is on to deliver the best IC process for today's chips. IBM aims to be the first to put a 0.13-micron process into production: Its CMOS-9S process will roll out in the first half of 2001, while Intel expects its 0.13-micron process around midyear.

Ultimately, a few months' head start is not that important. IBM's bigger advantage lies in the advanced features of its process, starting with the use of silicon-on-insulator (SOI) instead of bulk CMOS. IBM claims SOI boosts performance by up to 35 percent while lowering power dissipation.

IBM is the only company with SOI in production, and it looks to be two to three years ahead in that area. Although others plan to adopt SOI, Intel says its studies show little benefit from that technology. In fact, Intel's new transistor doesn't need SOI to achieve its superfast speed.

IBM's new process also features the material SiLK BEOL, which has the lowest dielectric constant in the industry. The local interconnect layer reduces SRAM cell size by about 15 percent, an important consideration given the large amount of cache on many modern processors.

Linley Gwennap is principal analyst at The Linley Group, a technology analysis firm in Mountain View, Calif.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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