Differentiating features, performance pushed to the limits, power cut to minimum-these are just three keys to success. The solution? Configurable DSP SoC design platforms, which provide configurable cores, configurable system architecture, customizable instruction sets and an easy-to-use design environment that works on the system level. No "fixed" DSP core can hold a candle to this approach, to say nothing of standard DSPs.

The successful DSP SoC design starts with the design environment. After a core is chosen, the design environment must support optimal design of the on-chip system bus, memory and peripheral interface subsystems and clock tree. These issues demand a highly integrated approach that combines a configurable DSP core with a flexible system bus and complete suite of DSP-based hardware and software tools.

Though enabling fully configurable systems, the design environment must ensure that a tested system architecture will result, reducing risk and shortening time-to-market. Environments fulfilling all these requirements enable DSP SoC designs in a few weeks rather than the six to nine months associated with traditional SoC designs.

The largest part of the die area-and therefore the biggest production expense-is the on-chip high-speed memory. Configurable platforms enable the design to iterate memory design while the software is under development. This ensures that memory systems will not be overdesigned in silicon. Configurable design provides the ability to select the number of DSP registers or the maximum capability of the multipliers, which translates into die-size and cost savings.

The major design trade-off is between performance, power consumption and cost. The application dictates the minimum level of performance. Excess performance can be traded for power consumption by slowing the clock, halting the DSP core or, better, lowering the voltage and slowing the clock. A configurable design platform lets the designer make these trade-offs within tight product introduction deadlines, limited NRE budgets and increasing production-cost pressures.

To ensure a short design time and a first-time-right product, a DSP SoC design platform must enable system-level simulation-including software-before the hardware is available. A DSP SoC design platform also must enable instruction-set modifications and add-ons to push the software to its limits, in speed and in power consumption. Synthesis, compiler, assembler and debugger should work with all these modifications on the hardware and software sides-without designer's interaction-quickly and accurately. Such a platform will enable telecom apps, and they will change our lives.

Kan Lu is Co-founder, CEO and President of 3DSP Corp. (Irvine, Calif.), which licenses DSP Development Tools and High-Performance, Low-Power DSP products.