It's no secret where most FPGA vendors are going. They are gobbling up design starts that have been marginalized by the ASIC industry. This leads them to build larger and larger devices, while trying to keep the size from making the chips inefficient in design or implementation. That focus has led to massive improvements in routing resources, the addition of embedded SRAM and now, even embedded CPUs.

But for a minority of FPGA adepts, that is the wrong course. The champions of reconfigurable architectures point out that the real strength of field reprogrammability is in the hardware's ability to adapt to the task mix in nearly real-time. Relatively small parts can serve huge numbers of tasks by simply paging in new logic configurations as needed. Logic optimized for a particular task, maybe even a particular data set, can be vastly more efficient than, say, a 32-bit RISC core or a DSP.

Mainstream FPGAs, with a few notable exceptions such as Atmel's devices, do little to help this process and often seem to create barriers to on-the-fly reconfigurability. Mainstream vendors point out that, until recently, there haven't been important customers interested in on-the-fly techniques, and usually cite two reasons: The techniques are very hard conceptually, and there are no tools.

On-the-fly reconfiguring techniques have been used for several years in audio mixer panels, they're central to Carver Mead's Foveon electronic-camera design, and they're being actively used by companies such as Quicksilver, Chameleon and 802 in new products.

The part about tools is a chicken-and-egg problem. If an earnings-growth-obsessed tool vendor saw a market, there would be tools of some sort this summer.

The more serious problem is conceptual. You can't get a good reconfigurable implementation by chopping your previous design into bite-size pieces. You must start over, with requirements, behaviors and algorithms, and work out a solution. That shortage may be what's keeping the FPGA guys from realizing the latent, explosive value in their product lines. It's also what's keeping designers from a powerful alternative to messy system-on-chip designs or expensive platform chips. Sometimes a good dose of training comes before either chicken or egg.