It has been common practice to use only register-transfer-level (RTL) models written in Verilog or VHDL. HDL-based flows and tools are used to further define and debug designs. However, the challenge of accurately implementing SoC designs on schedule has increased significantly with their growing size and complexity.

There's an active debate under way on how to best bridge the gap between system-level design and hardware implementation. Efforts to extend capabilities of existing HDLs to better define and verify the architectural level of designs is an obvious benefit for the many engineers well-versed in using HDLs.

Alternatively, since SoC designs typically contain a significant software component, it has become critical for complete and consistent models to ensure that hardware and software elements ultimately match. Expanding C++ to support hardware design concepts, like concurrency and time, would address the need for higher-level models and enable system architects to better examine trade-offs between software and hardware implementations.

At first glance, one could simply map tools that support C++ to an existing HDL-based design flow. There are numerous free or inexpensive simulation tools available to simulate designs, and lint tools to check C++ language syntax.

But specialized rule checking is needed to support code refinement when the design proceeds from the architectural to the behavioral and RT levels.

Lint tools prove insufficient, since a designer can write syntactically correct C++ code (so that it compiles without errors) while semantics needed for hardware design are not recognized. Those errors are found at run-time, with resultant behavior ranging from run-time error messages to a hung simulation or core dumps. All of that is unacceptable.

This issue does not exist in an HDL-based flow. Verilog and VHDL were created specifically for hardware design-the semantics are "built in."

Expanding C++ for SoC design shows great promise. But let's not overlook the details. There's a need for robust rule checking that includes coverage for hardware simulation semantics and synthesis rule sets. The tedious task of reviewing code could quickly deter any designer from reaping the benefits a flow based on C++ may provide.

MIke Baird is President of Willamette HDL Inc. (Beaverton, Ore.).