It's not easy to find an original meaning for SoC. Clearly it was never intended to be literal. After all, systems include passives, power supplies, electromechanical or electro-optical components, packaging and other items that cannot be integrated onto a single die, at least for now.

Nor could the phrase mean that all the purely electronic components in a system are to be on a single chip. Pry apart your cell-phone handset, and there will be, arguably, a system-level IC surrounded by a hive of active and passive components.

The more examples we look into, the more our definition loses force, until we are left with something like: "An SoC is a chip that integrates a large portion of the important electronic stuff for a system." Of course by that standard, the Dragonball MCU in a Palm Pilot or, to tax one's memory, the TMS 1000 MCU in the TI Speak'n'Spell would be an SoC. Cheers from microcontroller marketing folks notwithstanding, that is not a useful definition.

It might be more productive to look not at the chip, but at the design team who created it. Design teams who are working on system-level chip designs seem to have certain things in common. To float a sweeping generalization, the chip architectures designers refer to as SoC tend to resemble the systems architectures of a generation ago.

If you look into an SoC design, you are likely to find a number of separate processing and memory modules. Many of these structures will be connected to a chip-level system bus, which may become a design module in its own right. Almost inevitably, at least one of the modules will have significant mixed-signal content that is central to its function. And some of the modules will have been designed outside the current design team.

You might object that many of these elements occur in everyday chip design. True. SoC refers not to a particular size of chip or kind of chip, but to a design style. And that style is spreading rapidly throughout the ASIC-designing and FPGA-using world.

It is time for the design teams who pioneered system-level chip design to pass on their hard-won knowledge. This is beginning already in small ways, as papers are published, tools intended for huge multiprocessing chip designs are refined for smaller undertakings and as third-party intellectual property becomes more accessible. Another step in the process will take place March 19, when CMP Media, EE Times' parent, convenes the first industry conference aimed at disseminating the skills of SoC design to mainstream designers: IP/SoC 2001. I hope to see you there.

Ron Wilson is publisher of Integrated System Design magazine, a sister publication of EE Times based in San Mateo, Calif.