Modern IC design is similar: Engineers use C/C++ for system modeling and software development, Verilog and VHDL to produce tapeouts, other languages for verification and test, and SystemC as cocktail-party gossip.

This language, according to the SystemC Web site, is "a modeling platform consisting of C++ class libraries and a simulation kernel for design at the system-behavioral and register-transfer levels. Designers create models using SystemC and standard ANSI C++. EDA vendors create tools that are automatically interoperable."

But the evidence that any real chips have been designed using SystemC is scanty. As long as designers are getting the job done with their "native" language, there is little reason to change.

Chip design, like speaking a foreign language, is quite complex. Minor mistakes in translation can have major consequences. Being intimate with a language is something good Verilog coders are proud of. Over time, using an HDL becomes as natural as speaking in one's mother tongue. A fluency and familiarity with the particular vernacular of the language develops. Designers cherish its idiomatic ways and celebrate its subtlety. These engineers use Verilog to give voice to their ideas, using the language to express the intent of the design just as surely as a composer uses notes to create an artistic vision.

SystemC backers want everyone to use one form of expression to design a chip. In reality, engineers like to use the best tools for the job, including the language that expresses design intent best.

Design groups should continue to employ different languages on a single project for different tasks-C to explore and validate the system ideas, and Verilog to build silicon and guarantee tapeout. The notion that one language can do everything is unrealistic. It supposes a level of flexibility and descriptive power combined with implementation independence that isn't there.

Some language upgrades, like Superlog, show promise. By building on the successful legacy of Verilog it adds "system punch" to a proven language that has enjoyed many years of success.

When I talk to my colleagues designing 20-million-transistor circuits and planning for the billion-transistor devices of tomorrow, one thing is clear: They have no interest in basing their success on any universal language that may have political momentum but fails to deliver results.

A single language for chip design is, like Esperanto, another false promise.

Bernd U. Braune is Chairman, President and Chief Executive Officer of Get2chip.com Inc. (San Jose, Calif.).