One exception to that comfortable generalization arrives with the block-oriented, hierarchical design style that is now nearly synonymous with SoC design. If you partition the design into functional blocks-or if your acquisition of the major blocks from others partitions it for you-you are left with the problem of how to interconnect them.

The obvious answer, the one that has been right since the first transistors were getting wired together to make the first quad-NAND gates, is point-to-point wiring. Each block has its input ports and output ports, and by the time you have done even a coarse trial routing of a block you know about where those pins have to be. So you put the blocks down on the chip and hook 'em up, maybe about the same time that you put in the global clock trees and power metal.

Naturally something this simple couldn't last. A couple of problems present themselves right away. No matter how careful you are at partitioning, you are likely to end up with a bunch of runs between blocks lying in critical timing paths. That means that your timing closure may depend on your ability to control the length and parasitic capacitance of runs that can take off and wander halfway across the die. Not good.

Even if your methodology can insure you against timing-closure problems caused by interblock runs, there are more structural issues. Most SoC designs are CPU-centric, like the board-level designs they are superceding. That means the interconnect between blocks is already defined for you, in the form of a microprocessor bus, a peripheral bus or perhaps a derivative bus intended for on-chip use, such as Amba. But the world of on-chip interconnect is vastly different from the world of board-level buses.

Alternatives to on-chip buses are starting to get a lot of attention. One possibility now being seen in the communications world: crossbar switches. Using switches in place of a bus not only increases the maximum bandwidth but can make the interconnect much more regular and predictable. Other ideas are being imported from the supercomputing world. Rings, arrays and octagons have been suggested, and sooner or later someone is going to try a hypercube.