In boom times, all companies do well. It's more difficult to show profitability and growth during a downturn. The spoils go to companies with the best combination of market insight, technology and execution. And the key to execution is having the tools and methodologies to guarantee first-time success and minimize time-to-market. Companies that improve their design processes during a downturn are well-positioned to ride the next wave of growth when the industry recovers.

The last significant downturn, in 1996-97, occurred when commodity products dominated the industry: microprocessors and DRAMs. A very different class of device drove the recovery in '98: high-margin ASICs and mixed-signal front ends for the telecommunications and data-networking markets. At the same time, significant gains in productivity resulted from developments in the design automation industry, which simplified and sped up the specification and synthesis of large, complex, high-performance ASICs. The availability of new tools and methodologies was a significant enabler in the industry's rapid recovery and the growth of these new markets.

The cycle is about to repeat itself, possibly as soon as the fourth quarter. Although we may not know what the next big market will be, or exactly when it will occur, we can be sure that it will require system and IC design tools that exploit deep-submicron technologies to provide low cost and high performance, while supporting high-complexity digital and mixed-signal design-without sacrificing quality, time-to-market or flexibility. We can also expect to see changes in the organization of the design process.

Going forward, the EDA industry must focus on key challenges to achieve these changes. They include managing and partitioning the design of complex systems-on-chip, and managing design and verification of mixed-signal and large digital chips at 0.1 micron and below.

Also vital will be exploiting new opportunities in wireless, based on integrated passives. While low-cost, high-performance RF front ends will be achieved by eliminating off-chip components such as inductors, transformers and filters, the industry needs new tools to enable the accurate modeling and seamless integration of those components.

It will be key to synthesize complex systems from higher-level behavioral models based on generic (such as C/C++) or domain-specific languages. It will also be important to integrate board, package and chip design.

With rising frequencies and shrinking geometries, package and board/substrate parasitics become an essential component in the design of high-speed electronic and optoelectronic devices. New tools are needed to accurately model those components and incorporate them into the high-speed design flow.

Key advances in tools and methodologies would enable the companies that correctly identify the next wave to ride it successfully to market.

Bryan Ackland, the circuits and systems research vice president at Agere Systems (Allentown, Pa.), was chairman of the 39th Design Automation Conference.