But the conference and floor show seemed subdued, as if the real activity-like Intel's response to Pat Gelsinger's keynote plea at February's International Solid State Circuits Conference-was elsewhere. "We don't know how to cool a [projected] 5,000-watt processor," the Intel technologist told ISSCC.

Technical sessions at the Developer Forum concentrated on networking, multiprocessing and memory architectures. The papers and tutorials dealing with power-dissipation issues are more likely to appear at the Intel Technology Symposium, Sept. 27-28 in Seattle. It was as if everything I saw on the show floor was really a software pointer to something else.

Intel has been using clock throttling as a power-saving technique for its portable Pentiums, as well as forcing them to operate at a lower voltage. By altering both the voltage and the clock frequency according to the specific processing task at hand, it is possible to pull out only enough battery power to get the job done and then drop back into some sort of power-conserving sleep mode. While it literally forces you to count and prioritize clock cycles, this is the idea behind Intel's Mobile Voltage Positioning spec. IMVP calls out four operating modes corresponding to various power-consuming states: performance operating mode, the more modulated battery operating mode, deep-sleep mode and "deeper sleep," sometimes referred to as "near death."

IMVP2 supporters, like Analog Devices, put their voltage regulators totally under control of the Pentium host. Parts like the ADP3203 provide up to 40 amps of output current with pin-selectable one- or two-phase operation, and overvoltage and reverse-voltage protection. The next-generation regulator-one that supports a still-secret IMVP3-will include three-phase operation and support core voltages less than 1 V.