The growing tool support for phase-shift masks and optical proximity correction (OPC) is bound to have profound importance to custom-design teams. According to tool supplier Numerical Technologies, by use of phase shifting and OPC it is possible reliably to fabricate 70-nanometer gates in, for example, UMC's 130-nm process.

This means that custom cell designers using commercially available tools can create cells with substantially better performance characteristics than those of the standard-cell libraries for the process.

It is entirely possible to create a set of standard-cell libraries using these same tools and enjoying the same benefits. In fact, library vendors such as Artisan and Nurlogic are reportedly doing exactly that right now for UMC's 130-nm process. But the design work is not trivial. It requires both new cell designs and new packing rules to keep the phase shifters and OPC artifacts from conflicting with each other. So standard-cell libraries using the new transistors will lag behind the underlying process.

However, memory arrays and FPGAs make up regular arrays of fixed cells-an ideal situation for the Numerical tools. Major FPGA vendors may be able to speed up their memory and their logic elements before standard libraries are available, helping to close the gap between FPGA and cell-based ASIC performance. But only a little. Stage delay in FPGAs is dominated by interconnect delay, not by the logic elements. And the optical techniques don't change metal pitch or speed up the pass transistors that dominate programmable interconnect. So the new optical techniques are helping the wrong part of that problem.

There is an interesting exception, however: programmable logic arrays with mask-programmed interconnect. This is a rare architecture, at the moment represented by only a few devices, such as Altera Corp.'s Hardcopy chips (intended as an alternative to ASIC migration) and the programmable architecture from eASIC Corp. (with which, in the interest of full disclosure, this author used to have a business relationship). The eASIC designers and Numerical engineers have in fact worked together to create a paper design using 70-nm gates in the UMC process, and claim substantial performance gains.

If this work bears out, it could cause the entire ASIC business to once again rethink the question of logic granularity, and perhaps to swing back toward larger, configurable and more regular cells that can take advantage of sub-wavelength techniques before standard-cell libraries can.