There are few guarantees in broadband life outside a Gigabit Ethernet or 10-Gbit Ethernet physical layer. In the backplane-replacement world, high-speed interconnect players still need to place HyperTransport and Rapid I/O bets (with the advantage skewing toward HyperTransport). In metro topologies, resilient packet ring advocates are still caught between Aladdin and Gandalf RPR, with no clear winner in sight.
The only dependable chip interface implementation, then, seems to be the SPI-4 standard defined by the Optical Internetworking Forum. With its ability to handle 10-Gbit Ethernet, OC-192 Sonet and packet-over-Sonet, the System Physical Interface Level 4 standard seems to be enough of a commodity bet to justify both standard chip sets and perhaps intellectual-property (IP) cores.
Phase 1 of SPI-4 describes a 64-bit, single-ended interface between physical and data-link layers, clocked at 200 MHz. Phase 2 specifies a 16-bit interface using low-voltage differential signaling I/O, supporting 622 Mbits/second per channel. Both versions can support multiple physical-layer channels, with flow control mechanisms that support channelized and nonchannelized operation.
PMC-Sierra Inc., long a supporter of Saturn and packet-over-Sonet-PHY devices for high-speed Sonet, launched its first SPI-4 Phase 2 chip program in April, leading a wave of chip-set introductions that filled the summer and early fall. As early as the end of April, however, there was already a suggestion of the strong role IP cores would play in the SPI-4 evolution.
Xilinx Inc. and Applied Microcircuits Corp. jointly announced completion of the Flexbus 4 cores to support both Phase 1 SPI-4 and AMCC's own Flexbus standard. Modelware Corp. in July announced new SPI-4 cores to support Altera's Atlantic interface. They comply not only with SPI-4 but also with AMCC's Flexbus 4.
Because SPI-4 requires expertise in low-voltage swing logic as well as advanced Sonet and 10-Gbit Ethernet interfaces, IP cores for the standard are less likely to become commodity items than the cores developed for aging interfaces like PCI. Vendors could have a competitive field day with SPI-4 next year.
Silicon Logic Engineering Inc., a Wisconsin ASIC and core supplier spun out of Cray Research Inc., claims to have the first fully characterized Phase 2 core for SPI-4. And in mid-November, LEDA Systems (Plano, Texas) introduced the LaSer IP core suite for serial-link transceivers. The cores are compatible with both SPI-4 phases as well as the gestating SPI-5.
Maybe SPI will give the core community the high-speed kick in the pants it needs.
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