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WILSON_RONOnce again, this week it's time for the annual parade of semiconductor processing and test equipment at SemiCon West. We will get the latest on the host of processing equipment, nearly all of which is fascinating from an intellectual standpoint, but most of which has little or no interest to the chip design or chip-using community. Or at least that used to be the case.

Many of the things going on in the process and equipment area-especially in production test-are no longer just interesting amusements for IC design teams. Slowly but surely, the impermeable membrane that protected a chip design team from having to know anything about the foundry is breaking down. Details of fabrication, assembly and test are starting to intrude, first into back-end design, and eventually into even architectural planning.

A couple of obvious areas are the rapid changes in packaging and test technology. Many of today's high-speed I/Os are so fast that it is mandatory to model the package and board along with the pad ring to get an accurate model of the I/O performance. But the package models, unless you are lucky enough to work in a shop that designs, manufactures and assembles its own, will depend on decisions made by managers and machine operators in another hemisphere.

Similarly for test, the whole strategy for testability of a system-on-chip-set clear back at the architectural level-depends on details of the test equipment and allowable test time. If the test vendor has available high-speed digital and mixed-signal testers and racks of RF gear, it may be business as usual for the chip design team. If it's necessary to push an RF/mixed-signal, high-speed SoC through a conventional test floor, the design team had better understand the issues up front. And no one can afford to ignore the growing debate about the effectiveness of DFT-aware testers.

As we go forward, the fine structure of the chip-manufacturing process will also come into play. The ability to form features on the die is rapidly replacing random contamination as the primary cause of chip faults. The only obvious way around feature-formation problems is to pre-compensate for them in the design: not just in obvious ways such as optical proximity correction, but in adjusting large structures and even in making architectural decisions to head off hard-to-image shapes. The design team may end up having to know the peculiarities of particular steppers, planarization and deposition equipment in order to have some control over yields. Welcome to yet another dimension of design.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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