There are two basic mechanisms for this problem. First, with increasing integration, more and more of the nodes that test engineers need either to control or observe are actually on the IC, and hence not directly available after packaging. This is the more familiar part of the problem and is slowly being addressed by increased efforts in design-for-test. But even now, DFT discussions almost always center on the chip test issues, not on the needs of the board or system test folks. So, key problems can remain, even after a good job of chip-level DFT.

The second part of the problem is that with higher integration comes higher pin count, and with that come fine-pitch ball grid array packages, dense multilayer circuit boards and, not incidentally, more lightly loaded, lightly driven signal lines running at lower voltages and higher frequencies. This trend is making it difficult for test engineers to get at even signals that are external to the IC. And even if the signals are sort-of accessible, they are often nearly impossible to probe with anything short of a Star Trek Tricorder.

As a result, there is more and more talk about a radical idea: including not just scan or DFT circuitry on the SoC die, but in effect whole pieces of test equipment. These functional blocks can be developed as intellectual property and dropped into an SoC design in a strategic spot to give test engineers control and observability of key nodes. The nodes can be on the die or, increasingly, on the board but accessible only to the SoC.

Not surprisingly, the movement is starting in the digital domain, beginning as an evolution from ubiquitous on-chip CPU debug facilities. ARC Cores, for one, last year found that some customers were willing to pay a noticeable price in die area to pack a sophisticated logic analyzer into their chips.

Don't be surprised if the trend spreads to mixed-signal devices, such as signal generators, scopes and time-domain reflectometers. From there, with increasing integration, it could move to RF instruments and full network analyzers on the chip.