The latest technology brings the usual benefits: increased gate count, higher clock speeds and, in some cases, reduced power and chip cost. But that first chip is a doozy: Mask fees and other up-front charges can add $750,000 to the cost of the first 0.13-micron prototype.

As gate capacity rises, the trend is to integrate more functions onto a single ASIC. Even as design teams grow from a handful of engineers to a dozen or more, the schedule can easily extend.

Verification is the next problem. Not only is a complex design harder to validate, but the level of testing also has gone up. With tapeouts so expensive, the pressure is on to get it right the first time. Testing the design in an array of expensive FPGAs has become a standard procedure for leading-edge chips.

When tapeout finally happens, it means more than writing a big check. It means waiting and waiting some more. With the latest processes, cycle times are typically two to three months-another good reason to get the first design right. For all of those reasons, most system vendors are reducing the number of ASICs they are designing. This decision can cut development costs and get systems to market sooner, two critical success factors in a challenging business environment.

One way to justify a leading-edge ASIC design is to spread the up-front costs across a greater unit volume. In networking, a giant like Cisco can still afford to do ASIC design, whereas smaller competitors cannot.

But the best way to amortize up-front costs is to sell chips into multiple systems. Thus, we continue to see a boom in vendors that sell application-specific standard products to replace ASICs. As ASIC costs rise, the ASSP business model becomes more attractive.

In networking alone, dozens of chip companies are vying to sell ASSPs to equipment makers. With several choices for any function, these OEMs have fewer reasons to design their own chips and many reasons not to. Thus, we see the ASIC-to-ASSP conversion accelerating despite-perhaps even because of-the economic downturn.

Linley Gwennap is Founder and Principal Analyst of the Linley Group and co-author of "A Guide to Network Processors" (www.linleygroup.com/npu).