At the International Electron Devices Meeting in San Francisco earlier this month, power was the hot topic, starting with Andrew S. Grove's thoughtful remarks.

Power consumption is the major technical problem facing the semiconductor industry, said Grove, with off-state leakage current "becoming a limiter of integration."

David Frank, a physicist and member of the research staff at IBM's T.J. Watson Research Center, gave an invited IEDM address that was particularly honest.

"We often hear about the end of scaling, about hitting the brick wall. But that is not the right way of thinking about it. When a climber gets to the top of the mountain, he stops. Each application may have its own mountaintop of optimum scaling," Frank said.

"We need to talk more about the total cost of our systems, including the cost of the power, the utility bills and batteries," Frank said after his IEDM presentation.

The problem is that as device scaling continues to atomic levels, a higher percentage of power is wasted as leakage current. Dimension scaling has proceeded faster than voltage scaling, and there are physical limits to how much threshold voltages can be reduced.

And clock circuits run too hot: Frank estimated that about half of active power consumption is given over to clock circuits, an area with much room for improvement. Wiring densities can be improved significantly, he argued, reducing power consumption in many designs.

Scaling cuts per-transistor active power consumption, but leakage and the higher number of available transistors/millimeter2 keep pressure on the power budget. "My gut feeling is that designers will keep populating their designs with more options," he said, raising transistor count.

High-k gate oxides may cut leakage currents by about a third, and clever designs can help. Processes with multiple threshold voltages, based on different oxide thicknesses, "are the direction things are going already." Indeed, Frank noted, designers of Palm-like systems already must decide "how much performance they can cram in," given their power budgets.

Increasingly, designers will need to choose the best gate length, and perhaps limit the number of transistors, to deliver affordable, power-efficient systems.

"We should realize that there may be an optimum underlying device that is part of a systemic approach to power, including circuit and system design optimization. The cooperation of different engineering communities will be necessary," Frank concluded.

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