This may be the year of the low nonrecurring expense. With mask costs approaching escape velocity and funding for design teams approaching zero, a design manager has to minimize dollars-to-production. In low-volume or uncertain-volume applications, that means FPGAs. But in the applications that require ASICs, for cost, performance or power reasons, the picture has been less clear.
One answer, from AMI, Lightspeed Semiconductor, NEC and (to some degree) LSI Logic, has been sort of a super gate array. In these devices, predefined arrays of complex logic cells-or in LSI's case, whole blocks of intellectual property-are fabricated on a base array and warehoused. The base wafers are customized with the upper metal layers.
There is another path to the same end that may have very significant advantages for some design teams. It is, believe it or not, the old and much-discredited idea of the mask-programmed FPGA.
Such arrays have been offered, off and on, for years by all the vendors of SRAM-based FPGAs, always as a volume migration path for FPGA users. Hardly anyone ever thought of using them as a design target in the first place. However, the idea bears consideration.
In the case of Altera's HardCopy arrays, at least, the die is an array of FPGA cells, but with all the programmable elements replaced with metal segments in the upper metal layers. That gives a much smaller die, along with higher performance and lower power. Sound familiar?
Just like the cell array products, HardCopy is a warehoused base wafer that is characterized to a customer design during back-end processing. But unlike the other products, it is logically congruent to its parent FPGA. So it has an existing tool flow and prototyping platform-the FPGA and its tool chain.
The only thing missing is the timing and power-estimation tools that would let a designer target a design at the mask-programmed part from the outset. But Altera is said to be considering making those tools available in the next release of the company's tool chain.
That would permit a design team to employ the Altera tools to implement a design in the mask-programmed parts, just as they would do with the AMI, Lightspeed or NEC products-but with all of the tools, infrastructure and support that has grown up around the FPGA business. In effect, it would make the large SRAM-based FPGA vendors key players in the emerging segment of the ASICs market-just without their FPGAs.
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