One example is the cell phone handset market. Here, space and power demands need no explication: Everyone would be much happier if the digital radio, control processor and memory could all go on the same die. But it is instructive to note that this is not the path the industry is taking. Instead, there is a strong move toward stacked-die chip-scale packaging.

The Japanese, with their tiny and incredibly memory-hungry i-mode phones, are leading the way. And they are stacking a mix of memory types-masses of flash, chunks of SRAM or pseudo SRAM and, occasionally, DRAM-into chip-scale modules. In these packages the dice are back-lapped to 3 to 5 mils-so thin that the wafers are actually flexible-then glued together and connected by wire bonding to the exposed bonding pads on the edges of the dice. Crude, but effective.

Nor is the process stopping with memory. Intel is trying to pry open what has been an ARM-dominated market for mobile devices by including its StrongARM-derived Xscale CPU in the stack along with the memory. It is just a matter of time until a system OEM puts its own system-on-chip in the stack, creating, if you will, a system-in-a-pile.

All this has several important implications for chip designers. First, because of the extremely dense packaging made possible by stacked modules, the technology opens up serious alternatives to the old treadmill of more integration, harder processes and more inappropriate mixing of technologies. But the fine print is important too.

The simple stacking-and-edge-bonding approach requires careful attention to power dissipation and heating; capacitive coupling to what will now be adjacent chips; die form factor and size (to permit access to the pad ring inside the stack of dice); and proper pinout to keep the problem of interconnecting the dice within the reach of wire-bonding reality.

IMEC is researching an even more aggressive approach. The research institute is covering both surfaces of dice with bumps-C4-style-and using the bumps to interconnect the dice. The technology requires through-wafer vias, metal on both sides of the wafer and, clearly, a whole new set of back-end tools.