Fundamental change may be coming to the way ASIC and COT design is done. The change is already under way in what EE Times had been calling the structured-ASIC segment.

Here, designs are built on base wafers that contain predesigned arrays of logic cells. The products have all the advantages that gate arrays once had: low NRE, quick time-to-production and, at the same time, good performance and density. But they have been updated to the realities of modern processes: more-complex logic cells instead of a sea of gates, and richer interconnect.

That segment is about NRE and time-to-market. There is another trend that is just showing up in the technical papers that promises to be even more pervasive-and it is based on the ugly realities of 90-nanometer and smaller processes, not just the need to save on mask costs. This trend doesn't have a name yet, but it's been hinted at by such terms as "logic fabrics" and "radically restricted design rules."

The underlying issue is that it's becoming nearly impossible to deal with all the rules that advanced processes place on physical design. Forget signal integrity, leakage and IR drop. Think about pattern-dependent process variations that change the shape of-or simply leave out-features depending on what's around them. Or pattern-dependent thinning of metal and dielectric films, or rules that dictate the pitch of parallel features over a span of several dozen cells. These very real possibilities will make physical design a nightmare.

In response, researchers are glimpsing a future in which design rules will simply lay down a grid onto which all features will have to be set. Or, in some views, super-designer teams will produce a small number of predefined base arrays in which devices, poly and lower metal layers are pre-established and known (by sad experience) to work. Designs will be mapped onto that fabric.

Within a few years, the days of starting from a clean sheet of silicon may be gone for all but a handful of CPU and memory design teams.

Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process. he can be reached at rwilson@cmp.com.