There has also been work going on for some time indicating that memories play a major role in system energy consumption. It's now clear that this role is the dominant one. Time spent on optimizing memory activity can have a greater impact on dynamic energy consumption than just about any other exercise. As we move to lower-voltage processes, the same can be said of leakage power-again based on the relative area occupied by the memory.

Also, there is a known, though much more architecture-dependent, linkage between memory architecture and system performance. In some recent designs the ability to work with a single copy of a piece of data, rather than copying it all over the place as it is processed, can have a greater impact on performance than any tweaks that can be done to the data paths.

So why would designers not be spending most of their time talking about memory design and optimization tools? Perhaps there are some reasons. First, most of the optimizations that benefit memory structures need to happen at the architectural stage of design-the place where there are the fewest tools, and hence where designers are most on their own initiative. Second, the very fact that embedded memory has been so well supported by a few intellectual-property vendors means that most design teams take a black-box approach to memory instances. They don't look inside. All the work done on improving memory structures for energy efficiency, testability or yield gains has to be done on the modest research budgets of a few memory IP vendors. Much broader investment goes into logic design.

But as it becomes more accurate to call ASICs big memory chips with embedded logic, this situation may have to change.

Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process. He can be reached at rwilson@cmp.com.