As more embedded processing applications are done with system-level ICs, much of the microprocessor conversation has centered on intellectual property (IP) instead of chips. When vendors unveil an architecture, they are as likely to speak of a new synthesizable core as to brag about a new IC.

That change has quietly put physical synthesis tools on the critical path of MPU evolution. Since many of the users of CPU cores prefer to do their own synthesis, a feature isn't a feature until an average design team can synthesize it and have some reasonable chance of timing, power and signal-integrity closure. That has become both a serious consideration in CPU core design and an indicator of just how far synthesis tools have come.

The very existence of companies like ARC and Tensilica is a proof point. A few years ago, only a processor design team would have tackled synthesis of a customized CPU core, and no one would have entertained the idea of letting software modify a core, then push the button and have a working placement pop out. Today, that is a practice.

Another case in point might be the Topaz core introduced by MIPS. The core is licensed as synthesizable RTL, with a number of options, including the ability to extend the MIPS instruction set by adding custom execution units. Fine. MIPS is known for clean hardware designs that make things easy for the design team at modest frequencies.

But Topaz is intended for operation at up to 550 MHz in some 130-nm processes. It uses an eight-stage pipeline to make timing achievable at those speeds. And while the core uses a scalar design without multiple, out-of-order dispatch or speculative execution, there are many of the trappings of modern high-end CPUs, including sophisticated branch prediction and nonblocking loads, a very fast multiplier and a full set of pipeline bypass paths.

Such a design is overflowing with opportunities for timing problems, not to mention the sheer amount of connectivity, which stresses signal integrity and routing tools. It is a tribute to progress that such designs are now within the reach of system-on-chip teams.

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