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Why gate counts don't count
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BIER_JEFF

Every so often, I get a call from someone who wants to know the gate count (or equivalently, the silicon area) of some embedded processor core. And every time this happens, I have to stifle the urge to say, "Why on earth do you care?"

The reason the question baffles me is that, in chips that use embedded processor cores, the area used by the core is almost always negligible compared with the area eaten up by memory banks. It's common for the processor core to consume only about 10 percent of the die area, with 60 to 80 percent consumed by memory. Thus, in typical embedded chips, the size of the core itself is just not that significant in determining overall chip size.

"But wait," you say. "Isn't it important to choose a core that helps to minimize chip size (and hence cost)?" Absolutely. But comparing gate counts isn't the best way to go about making this choice. A better metric to use for this purpose is processor memory efficiency.

Memory efficiency measures how much memory is required for the core to execute a given task. It includes both program (instruction) and data memory.

The core's architecture and instruction set exert a direct influence on its memory efficiency; the quality of the compiler can also play a critical role if portions of the application are written in a high-level language.

Because embedded chip size tends to be dominated by on-chip memory, the size of memory required by the core has a dramatic impact on the overall chip size-a greater impact than the size of the core itself.

To illustrate that concept, imagine that core A is 50 percent smaller than core B, but uses 30 percent more memory. Assuming that with core B the chip has an 8:1 ratio of memory area to core area, it turns out that the bigger core will yield a smaller chip.

As prospective core licensees become more aware of the importance of memory usage, perhaps core vendors will spend less effort promoting their svelte gate counts and more effort promoting the attributes that really count.

Jeff Bier is the general manager of Berkeley Design Technology Inc. (www.BDTI.com), a DSP technology analysis and software development company. Jennifer Eyre of BDTI contributed to this column.

http://www.eet.com





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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