System designers used to ASICs and FPGAs now demand that even standard chips have just the right processing power and I/O interfaces for their application. But it can cost $1 million or more to tape out a new member of a product family. How can a chip vendor meet market demands without spending a mint on tapeouts?

The trick is to aim high, then create additional family members by removing features from the initial product. When done properly, defeaturing can reduce both per-unit and tapeout costs-double savings.

For example, Broadcom introduced its first SiByte chip with two CPUs, 512 kbytes of on-chip cache, three Gigabit Ethernet ports and a HyperTransport interface. It later rolled out a lower-cost version with one CPU, 256 kbytes of cache, two Ethernet ports and no HyperTransport interface. Although Broadcom won't comment on whether the two parts use the same die, the only tool needed to design the low-end part is an eraser; it simply has one fewer of every key component. The "missing" features can be disabled in firmware, by blowing fuses on the chip or by not bonding out I/O signals to pins.

Unit-cost savings come from yield improvement. If either processor on a two-CPU die is defective, the defective chip can still be sold as a single-CPU device. In the SiByte example, a chip with a defect in any part of the cache, or Ethernet or HyperTransport interfaces, can still be packaged as a low-end device. Only a die with multiple defects or with a defect in one of the few remaining critical areas must be discarded.

In this scenario, the die cost of the defeatured parts is essentially zero, since they would otherwise be unusable. The trick is to sell as many of these low-end parts as possible without exceeding the number of defective parts produced; otherwise, the vendor must sell some fully functional devices as defeatured parts. Supply (yield) and demand curves can be kept in balance by adjusting the price of the low-end part.

Other possible examples of defeaturing include PMC-Sierra's RM-9200 and RM9100; Motorola's PowerQuicc 8560 and 8540; Intel's IXP425 and IXC1101; and Cavium's entire product line. Some products have a high enough volume to permit taping out a trimmed version that reduces die size, but with the trend toward boutique products, more chips will be designed for defeaturing.

Linley Gwennap is founder and principal analyst of The Linley Group (www.linleygroup.com) and co-author of A Guide to Control Plane Processors.

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