United Business Media EE Times


Search

HOMEMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSSMost Popular contentTrusted Sources

 


When 90 nm really means 170 nm
Print this article Email this article Reprints RSS Digital Edition

EE Times


LAMMERS_DAVIDChris Progler, the chief technology officer at mask vendor Photronics, was at Semicon West a few weeks ago, and I asked him which form of lithography might be used at the 32- and 22-nanometer nodes. Progler, who once managed IBM's optical-lithography development, laughed and said he thought the whole idea of "nodes" on the road map would "diffuse away" after the 65-nm generation.

Progler backed up his argument at a lithography seminar, organized by Dai Nippon Screen, saying that he has taken 10 so-called 90-nm devices, looked at the masks and discovered "enormous ground rule differences" among them.

The minimum half-pitch on the 10 logic chips ranged from 110 to 170 nm, Progler said, with none of them having a 90-nm feature anywhere. That drew a chuckle from his audience, as if Grandma had caught a few hands in the cookie jar.

Memory vs. logic
During Semicon West, nearly 100 people from the major chip-producing regions met to discuss the 2003 edition of the International Technology Roadmap for Semiconductors. Paolo Gargini, the Intel Fellow who serves as the ITRS chairman, said part of the challenge of defining a "node" stems from the widening difference between DRAMs and logic. DRAMs push lithographers with a half-pitch that is fast approaching 90 nm for the most advanced devices. And memories have fairly evenly spaced lines and spaces.

Logic has more single lines, with many more contacts, and a higher metal pitch. Also, logic vendors use etch-back techniques to shrink the actual gate size. "For logic, most companies do an average, taking the contacted metal half-pitch and the poly isolated line, and dividing by two," Gargini said.

Another way of looking at it is that a 90-nm logic device might have a half-pitch of 120 nm and a gate length of 60 nm, producing a device that qualifies-for marketing purposes-as a 90-nm chip. Gargini said scaling is determined by a company's return on investment (ROI) and competitive pressures. "If your ROI allows you to scale as fast as possible, why not go as fast as you can?" he asked.

I'm all for fast horses; it makes the semiconductor industry race more interesting. But how about that 170-nm half-pitch that is being pawned off as a 90-nm chip?

David Lammers covers SoC process equipment. Contact him at dlammers@cmp.com.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


  Free Subscription to EE Times
First Name Last Name
Company Name Title
Email address
  Click here for your Free Subscription to EETimes Europe
 
CAREER CENTER
Looking for a new job?
SEARCH JOBS
SPONSOR

RECENT JOB POSTINGS
CAREER NEWS
SRC Expands R&D Centers
The Semiconductor Research Corp has added a new center to its university R&D efforts.

For more great jobs, career related news, features and services, please visit EETimes' Career Center.


All White Papers »   

 
Education and
Learning


Learn Now:












Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
Network Websites
International
Network Features




All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC All rights reserved.
Privacy Statement | Terms of Service | About