A great deal has been written about the challenges of low-power design for battery-operated system-level ICs. It has been observed that at 130 nm, both active power and leakage power are serious considerations. Techniques under development to deal with the problem include clock throttling, which has been used for some time; mixing of high-threshold and low-threshold transistors in the design; and scaling the voltage of blocks to match their required performance.

But those techniques won't always take us far enough. To meet some requirements, it will be necessary not just to scale voltage but also to vary voltage dynamically between zero and operating maximum, depending on whether a block is idle, working on a noncritical task or working to meet a demanding deadline. That lets the designer make sure that each block is supplied just enough voltage to run just fast enough to get its job done in time.

Of course we are talking about digital logic here. Voltage scaling for memories is a much different subject, and for analog circuits even raising the issue can get one throttled by a team of enraged analog designers. But, for digital logic, the promise is to slash energy consumption without harming performance.

But first . . .

There are substantial chip design issues involved. To begin with, logic cells are generally characterized around some nominal operating point, or perhaps between process corners, not continuously from zero to some maximum voltage. So there is characterization work to do just to find out what the minimum voltage is for a given path delay. There are also signal integrity issues. In general, signal integrity problems lessen as voltage decreases-unless while your voltage is going down, the voltage on the net next to you is going up. In that case, you are becoming more susceptible to an aggressor that is getting louder.

Top that off with serious issues about interfacing between blocks whose voltages vary dynamically and separately from each other, controlling the stability of blocks during voltage changes-or during power-down and power-up-and managing a clock network across multiple dynamic voltage domains, and you have an interesting problem.

But the hardware problem may be nothing compared with the problem of finding out from the software folks just what the minimum performance for a given task might be. They are unlikely to have ever asked themselves that question.

Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process. He can be reached at rwilson@cmp.com.