How long will CMOS scaling continue? How long will the annual cost per function keep coming down at the historical rate of 25 percent?
Chris Mack, an Austin-based lithography engineer, believes that the 45-nm node may be a realistic limit to widespread scaling of the defined pitch. Mack authored a widely used lithography simulation tool, ProLith, and sold his company, called Finle, to KLA-Tencor, where he is vice president of technology.
He teaches a lithography course at the University of Texas at Austin, and notes that integrated circuits are defined by two metrics: their smallest feature size as well as the pitch, i.e., the line and space. (The 45-nm node gets its name from the half-pitch of DRAMs, so the 45-nm node has a pitch of 90 nm.)
"From a lithographer's viewpoint, there is a hard limit to the smallest pitch you can print," Mack said, explaining that the limit is governed by the wavelength of the light divided by the numerical aperture of the lens in the scanner. Beyond reducing the pitch, technologists have other knobs they turn to reduce the feature size, such as improving the line-edge roughness of the resist, improving etch control and several others.
Mack argues that while engineers will continue to improve process control for a long time, there are economic limits to how far the pitch can be reduced. Those limits stem from the cost of buying and operating the steppers.
"Basically, it is 193 forever," Mack said, with immersion extending 193 nm to the 45-nm node. That is a sweeping statement, because there are plenty of candidates waiting in line to replace wet 193-nm tools. Mack argues that while the problems with 157-nm scanners-that is, the lack of a soft pellicle-can be resolved, the answers will be economically unattractive.
Ditto, in spades, for the extreme-ultraviolet scanners, which Intel and others hope to be using by the end of this decade.
Will scaling slow down at the 45-nm node, limited by lithography? Mack's view is on the conservative side, but his point stands: The cost of scaling is becoming more important than the sheer ability to shrink.
With that in mind, the chip industry certainly needs to develop a consensus about what kind next-generation lithography will be viable in 2010 and beyond.
David Lammers covers SoC process equipment. Contact him at dlammers@cmp.com.
http://www.eet.com