It seems a good time to sit back and take stock of the changes that are working away beneath the surface of the industry. One of these, certainly, is the shifting fate of ASICs.

A few years ago-the bubble days-that future seemed clear. The best technical solution to making an end-product faster, smaller, more efficient and, ultimately, cheaper, was the solution with the highest integration. That meant system-level ICs. And that, in turn, meant highly application-specific systems-on-chip-the more of the system that goes into the chip, the more the chip must be specific to the system, unless you are very, very clever.

This entailed huge chip development costs. We recognized that, but given the growth projections for just about every market, the costs were easily justified. So we plunged into ASIC design in unprecedented numbers. Many design teams found conventional ASIC relationships constraining, and they leapt into customer-owned-tooling design.

We are in different economic times now, and chip design's growing costs don't appear so reasonable any more. Prophets of worry are suggesting that only a reasonable share of a billion-dollar market could justify developing an SoC in a 90-nanometer process. So a lot of rethinking is going on.

The knee-jerk approach would be for all but a handful of ASSP vendors to renounce chip design altogether, and learn to fit their aspirations into the procrustean beds of FPGAs and standard-product ICs. Another alternative might be to demand more flexibility of ASSP vendors, so that their products could be personalized after-or late in-manufacturing.

Still a third option is viable, but harder: Design teams can comb through their process, identifying where the costs are and systematically reduce them. If 90-nm tools and masks are expensive, get creative with 130 or even 180 nm. If verification is eating the design budget, improve the methodology. Modularize and rely heavily on reuse. Exploit multiproject wafers. Above all, control software development costs.

Many of the dire forecasts for the end of ASICs rest on worst-case estimates. They should not be tales of doom, but rather checklists for good fiscal management.

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