Rapid growth in the structured ASIC business appears to validate the following concept: Create a standard-logic fabric, reduce the user-defined mask layers to a few upper metal layers, and ASICs can be cheaper and quicker with minimal loss in performance or density. There are of course exceptions, often dealing with large hard-intellectual-property blocks, extreme clusters of timing-critical paths or anything to do with analog. But for many designs, the concept is useful.

It's a minimalist concept. But just how minimalist can it be? Most structured ASIC architectures use two or three interconnect layers, and the intervening via layers, to customize the chip. Several architectures are confining the user input to just via layers-in some cases just one via layer. There are advantages and complications to that approach, but the advantages make this a technology to watch.

The drawbacks are obvious. To handle all of the customer-specific interconnect with via layers, the metal layers must contain a pattern of predefined segments-not unlike the structure of an FPGA-that can be assembled to make any desired set of connections for virtually any mapping of logic functions onto logic elements. To do that, all the customer-specific signals must be brought up to the metal layers on either side of the vias. Those problems can be addressed by careful planning, standardizing cell contacts and making the logic elements themselves SRAM-configurable.

The advantages are compelling. For one thing, a via mask contains only one feature: a via. Checking is relatively easy, writing is fast and, at the relaxed geometries of higher metal layers, little can go wrong. For another, it has been shown that in a production environment, you can eliminate the via masks altogether and directly write the vias with an e-beam system. That reduces throughput but it makes it feasible to do production wafers with-in the extreme-every die implementing a different design.

Diverse players as eASIC Corp. and ViASIC, each of which uses a single via layer, and Synopsys MPFS, which uses three via layers, are all offering such designs now. Given the trade-offs involved, such architectures could make up an important subsegment of the structured ASIC business.

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