The structured-ASIC concept continues to gather steam, at least in North America. Vendors report increasing interest. And the segment is now being tracked by a number of analysts, with of course varying opinions about market size and potential. But one thing seems certain: Whether or not structured ASICs themselves become successful in the market, they have ignited a renewed debate about where the costs, in time and money, really are in ASIC development.

Vendors of conventional ASIC services are re-emphasizing their ability to turn designs very quickly under some circumstances. There is no way that a full cell-based design can be processed as fast as the top few metal layers in a gate array or structured device, but the difference may be smaller than you think.

Other differences in schedule need examination as well. Physical design is frequently considerably faster for structured devices, simply because the majority of the shorter, faster nets are placed, routed, extracted and verified when the base wafer is designed. But there may be an important lesson from this comparison.

The advantage of the structured devices in physical design is, in effect, a limited example of design reuse. Design teams that are able to heavily reuse intellectual property can slash huge amounts of time and money from their efforts. At a recent conference, John Yue, vice president of technology at TSMC, pointed out that while a large, from-scratch 90-nanometer design could indeed cost $25 million, a derivative design that reuses substantial amounts of a previous one could be done for a small fraction of that amount.

Another point worth considering is that design teams can save time and money by not pushing the envelope. Using relaxed design rules on more mature processes can save an enormous amount of time, especially during the back end of the flow. Designs that fully exploit 250-nm and 180-nm processes can be virtually pushbutton at this point, according to some experts. And often, particularly with some good front-end planning, those processes can get the job done.

The question isn't whether structured ASICs will win or lose by some arbitrary criterion. The point is that they have ignited a valuable discussion within the industry about design cost vs. end results. That can only help.

Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process (rwilson @cmp.com).