Bernie Myerson, chief technology officer at IBM Microelectronics, said that at 90 nm certain companies will "hit a performance wall and step over a power cliff. To deal with the power density on these 90-nm chips, at IBM we are developing holistic design techniques" to spread the risk among the process, circuit, system and software engineers.

Already, some companies are finding that as the wires get thinner and RC delays increase, they lose performance at the back end, Myerson said. So they fudge on interconnect scaling, thickening certain wires. "Some things no longer can be scaled, like the oxide thickness. Others cheat on scaling the voltage; they adjust the threshold voltage up to deal with the power density."

Mike McKeon manages a Denali Software team based in Austin that develops memory controllers, and he is finding that the 90-nm libraries are highly unpredictable.

"Up to 0.13 micron, everything scaled pretty linearly. There were some big changes for the process people, but for the design teams it was a relatively easy transition to 0.13. But at 90 nm, everything is changing. The 90-nm libraries are all over the board," McKeon said.

The problem is that the devices are leaky, and unpredictably so. "There is no back-of-the-envelope calculation you can make at 90 nm. I've worked on designs where I've been off by 30 percent and couldn't make timing," McKeon said.

At the Litho Forum in Los Angeles recently, one source said his company did a survey of its customers, added in data from the leading research companies and found that very few 90-nm designs are under way-far fewer than his company had hoped for at this point. "You can count the number of designs on your hands," this source said.

The 90-nm logic chips can have a half-pitch of perhaps 120 nm at the lines and spaces, while the effective length of the gate can be 45 nm. Logic vendors take an average of the two dimensions and say it's a 90-nm chip.

At the end of the day, it appears that 90-nm designs may involve more of these compromises as the industry struggles with real physical limits.

David Lammers covers SoC process equipment. Contact him at dlammers@cmp.com.