Much has been made lately about the spiraling cost of chip design projects, with numbers in the $20 million range being wielded like Nerf bats in an aggression therapy session. So much discussion has gone into the issue that it is well to step back for some perspective.

Million-dollar mask sets are easy to blame. But if the cost of the design is $20 million, even a $1 million set of masks is not the big problem.

A look at the breakdown of costs indicates that indeed the money is going elsewhere. It turns out that one of the biggest culprits is one of the least glamorous: verification. Not only is the verification process itself expensive in the number of dedicated engineers involved and the tool licenses required, but the time the rest of the team spends idling or trying to help while verification grinds forward is a significant part of the total schedule. Add in the cost of partial design iterations because late-stage verification turns up serious issues that early verification missed, and you have a real money sink.

That thought is corroborated by data from last fall's EE Times SoC Online conference poll. When attendees were asked which areas we should focus on for content next time, the most frequent response, by a big margin, was "verification."

Not that the area has been ignored. Verification-formal verification in particular-was the target of a flurry of startups a couple of years ago. Verification receives attention at the design conferences. Janick Bergeron continues to run a high-traffic and valuable Web conversation on the subject at http://verificationguild.com/.

But somehow none of this work seems to be reaching the critical mass that would turn verification into a solved problem. Designs continue to be planned with verification as an afterthought. Then, verification continues to gorge itself on design resources and schedule, every week smacking its lips and demanding more. More and more designs go to silicon when the project leader has run out of time, rather than when anyone believes those designs have been adequately verified. Worse, critical pieces of functionality get pushed into configurable logic or software, where they become almost inherently unverifiable, but easily modified.

That is a big chunk of money, and there has to be a better way.

Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process. He can be reached at rwilson@cmp.com.