But what is true for the controller can be true for a high-speed device directly in the path of Internet Protocol packets. For the last five years, designers of dedicated forwarding engines have assumed that the task of meeting physical-layer speeds at 1 and 10 Gbits/second would make it difficult for a multifunction, system-on-chip device to take over true network processor functions.

They were right about two things: The time is not yet ripe for a single processor that mixes control and data plane functions, as Broadcom tried to do with its SiByte architecture. Then too, dedicated coprocessors in the data plane have not been a stunning market success. A few CAM companies maintain a decent business in search engines, and integrated traffic managers can be part of a winning product suite, but defunct companies such as Fast-Chip and Acorn indicate the perils of addressing too small a niche.

Linley Group author Sanjay Iyer pointed out in his control plane study that there's no reason a specialist in wireless LANs or encryption couldn't build from a vertical base of expertise and add RISC cores for general-purpose management and channel aggregation. Programmable cores are so commonplace today, control plane aggregation may become a commodity business soon.

But why not in packet forwarding as well? IDT recognized this when it worked out from its base in MIPS cores and made sequential acquisitions of Solidium Systems for packet classifiers and ZettaCom for switching fabric and packet management. An NPU company specializing in deep-packet inspection would say that using multiple pipelined RISC cores to examine packet headers requires detailed expertise in parallelism.

Perhaps. But the future of the dedicated NPU could be limited in practice by the companies that develop products for dedicated end applications. Communication aggregators already are morphing into ASSPs, and NPUs could follow.

Loring Wirbel is Communications editorial director for EE Times and its network publications.