For years, device technologists and circuit designers could live in their separate domains without crossing paths. The two types of electronics engineers would develop the best devices and the cleverest circuits they could, then present papers at their respective conferences to brag about them. For the device researcher, the premier conference has traditionally been the International Electron Devices Meeting (IEDM), held every December; for the circuit designer it's the International Solid-State Circuits Conference (ISSCC) the following February.

With each passing year, the two conferences have offered increasingly complementary papers tracking the accelerating pace from development of a device to its implementation in a circuit as a functional building block. As long as the end system was your average desktop computer, there was wiggle room for both the device technologist and the circuit designer when budgeting power consumption. But with the dawn of the consumer electronics era--when the circuit is being designed for wireless handheld applications, for example, where every microwatt needs to be accounted for--no extra consumption can be tolerated. As new devices with novel combinations of materials are developed, technologists need to be frugal in designing energy-efficient devices to be used in a circuit, while circuit designers need to relay their specific power and energy concerns to the device developers. The more energy-efficient the design, the longer the circuit can operate under the specified battery life. Supply voltages need to be aggressively scaled in such applications to maximize energy efficiency. And that aggressiveness needs to be applied across the board, all the way down to the electronic-device level.

As the industry enters the optimization phase of 45-nanometer IC designs and starts looking at 32 nm, there is an increasing need for technologists and designers to know each other's fields. In an IEDM paper, "Lithography Challenges for 32-nm Technologies and Beyond," Intel fellow Swaminathan Sivakumar predicted that "in future process technologies, it will be absolutely crucial that lithographers and device and circuit designers plan a priori the precise details of design rules, layout methodology and device topology to ensure that the chip can be successfully manufactured." Otherwise, "device or circuit configurations that are lithographically challenging will have little chance of being patterned successfully."

Sivakumar concluded, "Lithography options for future technology generations are becoming increasingly difficult and expensive, and the final choice for any technology would involve both capability and cost-of-ownership considerations. Since many features do not scale well, co-optimization of device and circuit design and layout are absolutely essential to enable effective overall chip scaling." It was a clear call for interdisciplinary, cooperative development and design.

Already, the organizers of the Design Automation Conference and the ISSCC have swapped "best of" papers from each other's conferences. And on Feb. 12, the ISSCC for the first time will hold an evening session titled "Highlights of IEDM 2006." The sponsors describe it this way: "Both worlds, of devices and circuits, have so much in common that one cannot live without the other. In this special evening session, we try to bring both worlds together."

Here's to the start of a beautiful friendship.