At TSMC, Lin will have a chance to be an early adopter of immersion. The company expects to receive an ASML 1250i immersion 193-nm scanner in September. While most companies will put immersion into manufacturing at the 45-nm node, TSMC expects to use it for 65-nm logic-chip production.

During Lin's recent visit to Austin, I asked him what he thinks of maskless lithography, or ML2. Since TSMC makes so many low-volume chips for customers, maskless is a natural fit for the foundries.

Lin said he is studying the maskless optical approach, using digital mirror arrays, being pioneered by ASML and Micronic Laser Systems AB; and the multiple e-beam system being pursued by Mapper Lithography BV. "Only Mapper, in my opinion, has a design that avoids the space-charge problems common to multiple e-beam systems," Lin said.

Mapper has developed prototypes with about 100 beams, with a goal of 13,000 beams writing the circuit patterns directly on the wafer. The Delft, Netherlands, startup is in need of more funding to develop its ideas. But Lin said if the Mapper engineers can continue to demonstrate that the basic concept works, with a path to get to their speed and throughput goals, "they will get plenty of support."

The ML2 approach of ASML and Micronic also has technical hurdles. The digitally controlled mirrors Micronic developed for its mask writers are not optimized for maskless lithography. Again, critical-dimension control and throughput are the two metrics TSMC is evaluating.

"The selling point of optical maskless is that it is still an optical approach. The resolution could be slightly better than masked lithography, because, at subwavelength dimensions, we may see some distortions from the mask," Lin said.

Immersion 193 lithography will take the industry through the 32-nm node. Then maskless must be ready, Lin said, adding that he holds little hope that extreme-ultraviolet lithography will ever be affordable.

David Lammers covers SoC process equipment. Contact him at dlammers@cmp.com.