After about six months of work, the team figured out that depositing silicon germanium at the source and drain regions could improve PMOS performance by at least 30 percent. "It took us six months to figure out how to do it," said a member of the team. "It took another three and a half years, working seven days a week, to get it to yield."

When Intel first announced that it had used some form of strained silicon, the company was deliberately vague, saying that it got a major boost from a 5 percent cost adder. Only much later-at the International Electron Devices Meeting, in December 2003-did it provide details about its "uniaxial" approach.

Still, critics derided the process, postulating that it would suffer from poor yields. That now appears untrue: Intel says it will cross over in the third quarter, with a majority of its processors made on the 90-nm process.

Nonetheless, in May 2004, Intel said it was canceling its Tejas single-core processor project and moving to dual-core designs. Analysts issued reports asking "What's wrong with Intel's 90-nm process?" Nathan Brookwood at Insight64 got it right, saying the issue centered on the Prescott design.

A circuit design manager working in Hillsboro said he had voiced concern as long as two years ago that Prescott's deep pipeline would cause power problems. "We told them then that this would happen, that the pipeline was too deep and that they needed to go more in the direction of the Centrino architecture," the manager said.

Overall, Intel's process engineers deserve some credit for innovation at the 90-nm node: It would be counterproductive if Prescott's problems were used as an excuse not to invest in the innovations, such as strained silicon, that will be needed to boost clock speeds further, even in multicore designs. This country already invests too little in silicon research, and we don't need misguided excuses to cut back even more.

David Lammers covers SoC process equipment. Contact him at dlammers@cmp.com.