But, today, there is a growing consensus that the 6-T SRAM, after having survived for so long and steamrollered so many supposed challengers, is running on empty. "At the same time that the amount of memory necessary on an SoC [system-on-chip] is increasing at an unprecedented rate, the 6-T cell is getting very difficult to scale," observed Ludo Deferm, vice president of business development at the IMEC research institute. "On the plus side, the 6-T cell is easy to fabricate-it does not require any special steps. It is fast and its power consumption is acceptable. But it is not clear that it is a sustainable design much below 65 nanometers."

Low operating voltages, increasing leakage and shrinking area-reducing the capacitance upon which the stability of the SRAM cell depends-are all conspiring against the design. The first symptom has been a dramatic increase in soft-error rates for large SRAMs, leading library vendors to offer error-correction circuitry in their SRAM compilers. But Deferm and others believe this is just the tip of a problem that means the 6-T's days are numbered.

So, what is the alternative? Motorola, among others, has been vocal about the promise of FeRAM. But that technology has serious drawbacks, including unproven reliability and-the ultimate horror of process engineers-new and unfamiliar materials. It's possible that if FeRAM was in other regards the best solution, it would not be introduced simply because of the risk of process integration problems.

IMEC is looking at other possibilities. One is using high-k gate materials in a tunneling cell to make a 2-volt EPROM with 0.5-V read levels-a device that could be used as an SRAM. Another is to use a floating-body transistor in a silicon-on-insulator process as, in effect, a DRAM cell.

None of these is an exact replacement for 6-T SRAM. But in SoCs, one may be a successor.

Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process. He can be reached at rwilson@cmp.com.