Even more fundamental than those questions is whether power consumption issues will create a practical limit to device scaling. Indeed, we live in interesting times.

Take the lithography debate. Assuming that mask costs will continue to rise and the vast majority of chips will be used in highly cost-sensitive systems, then it may be true that 193-nm lithography will be the dominant wavelength for a long time. The 193-nm scanners may always be cheaper to operate than the extreme-ultraviolet scanners.

How about the high-k debate? Many technologists think we are at the end for silicon dioxide scaling. Intel's 65-nm process, for example, uses the same oxide thickness as the 90-nm node; one indication that a shift to high-k is sorely needed. But what if SiO2 can be thinned from 12 angstroms now to 8 angstroms by using a metal gate electrode? If customers would be willing to accept more relaxed reliability standards, nitrided oxides may be more extendable than some believe, perhaps through the 45-nm node.

And what about flash? Is it also at death's door? Process experts think they can extend it for three more generations, to 32 nm. Will multilevel cell technology work then? If it does, we might get to 32-Gbit NAND flash devices in the next decade before switching to, say, phase-change memories for the highest-density nonvolatile memories.

Taking today's familiar planar transistors further out also would be welcome, largely because it will be costly for designers to switch to the new libraries and EDA tools that will be needed to use the multigate devices in complex designs.

If we can extend the familiar longer than expected, the industry will transition to new materials and structures with far fewer disasters.

David Lammers covers SoC process equipment. Contact him at dlammers@cmp.com.