There is a growing conversation these days about verification intellectual property. A clear analogy to the concept can be drawn from design IP: Use prefabricated building blocks that you can just drop into your flow to perform a predefined function. But instead of becoming blocks of the design itself, verification IP blocks become parts of the testbench used in verification. Like other IP, verification IP can, in theory, be designed for reuse or licensed from third parties.

Accordingly, there is a fledgling industry in verification IP. A few startups are trying to make money at it. Some design services companies are trying to use the concept to package their expertise. By doing so they can create off-the-shelf, revenue-producing products without having to commit full-time engineering resources to each customer.

And slowly but surely, the EDA giants are beginning to realize that verification IP is just as vital to the success of their customers' designs as design IP.

But where verification IP fits in the market food chain is a difficult question. If the experiences of many entrepreneurs are common, verification IP is not going to be successful as a standalone product line. But then, neither was design IP, except in a few unique cases, where a large company reached down to anoint the IP vendor.

The right source
So should the verification IP come from the design IP vendor? This has the appeal of one-stop shopping. And who could know more about verifying a piece of IP than the original designer? Well, almost anyone, in the opinion of many once-burned engineers.

In fact, some companies have licensing guidelines that forbid acquiring verification suites from the design IP source. The problem is that the original IP developers have biases about the domain and range of the design-the number of ways it can be used and can be expected to behave-that are enshrined in the design itself. If those same biases are built into the verification IP, the verification flow won't detect any problems that the original design team failed to foresee-that is, all the important ones.

So if the verification IP shouldn't come from the design IP vendor, and isn't likely to come from third parties, whence should it come? Some point fingers at the EDA giants again, and suggest that verification IP, like commodity design IP, is destined to be a library that gets licensed along with the simulation environment. Or perhaps it will be a library attached to the synthesis environment, so the synthesis process can produce a testbench along with the netlist.

All this, of course, would require the EDA vendor to be an expert in the functions of the design IP but to be independent from its developers. Another alternative, at least for blocks that implement standards, is for the standards body itself to supply the verification IP along with the specification documents. It, after all, is supposed to be the final authority on how the block should work.

In one stroke, this move would strengthen the standard, make implementation easier and greatly facilitate verification. But don't hold your breath. The detailed, expensive work of constructing a testbench for an interface is the last thing most standards bodies want to get involved in.

Ron Wilson is semiconductors editor for EE Times. Contact him at rwilson@cmp.com.