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BrianBailey
Member Since: November 26, 2012
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IP Roundtable, Part 7: System-Level Prototypes
Blog  
9/25/2013   Post a comment
The concluding part of this experts' roundtable on IP cores looks at the issue of system-level modeling.
An Engineer's Progress, With Prakash Narain, Part 4
Blog  
9/24/2013   Post a comment
The fourth part of an interview with Prakash Narain, CEO of the formal verification company Real Intent.
EDA/IP Weekly Roundup: Sept. 23, 2013
News & Analysis  
9/23/2013   Post a comment
This is a condensed roundup of news and activities associated with EDA and IP over the past week.
Verification Panel, Part 4: It's About the Coverage
Blog  
9/20/2013   4 comments
The fourth and final part of an experts' discussion panel on verification tries to look forward and reveals that, as ever, it's all about the coverage.
An Engineer's Progress, With Prakash Narain, Part 3
Blog  
9/19/2013   Post a comment
The third part of an interview with Prakash Narain, CEO of the formal verification company Real Intent.
IP Roundtable, Part 6: Integration Issues Ahead
Blog  
9/18/2013   2 comments
IP experts discuss why there are no tools and few standards for the integration of IP blocks and what it will take to force the adoption of a more top-down approach.
EDA/IP Weekly Roundup: Sept. 17, 2013
News & Analysis  
9/17/2013   1 comment
This is a roundup of news and activities associated with EDA and IP over the past week.
An Engineer's Progress, With Prakash Narain, Part 2
Blog  
9/16/2013   Post a comment
What do you do when nobody wants to be CEO of the company you have founded?
Verification Panel, Part 3: Stretching Formal
Blog  
9/13/2013   2 comments
The discussion turns to the how far formal methods can go in addressing the challenges facing SoC design.
An Engineer's Progress, With Prakash Narain, Part 1
Blog  
9/13/2013   1 comment
In a multipart interview we examine the world of EDA and verification through the progress of Prakash Narain, the founder and CEO of Real Intent.
EDA/IP Weekly Roundup: Sept. 10, 2013
News & Analysis  
9/10/2013   Post a comment
This is a roundup of news and activities associated with EDA and IP over the past couple of weeks.
IP Roundtable, Part 5: Is EDA Unfair Competition?
Blog  
9/5/2013   Post a comment
Multiple instances of EDA tools are essential for IP core development. Do Cadence and Synopsys have an unfair advantage in developing IP cores?
Verification Panel: It's More Than the Hardware
Blog  
9/2/2013   1 comment
In the second part of a panel discussion on SoC verification, Gary Smith raises flags and warnings with industry experts about how complexity now bridges hardware and software, and how continuity is breaking down.
IP Roundtable, Part 4: Standards, or the Lack of Them
Blog  
8/30/2013   Post a comment
We listen in on the IP roundtable discussion that moves on to the topic of standards for IP.
Verification Panel: Are We Done Yet? Not Even Close
Blog  
8/27/2013   2 comments
Discussion panels held in public are often dull exercises in easy harmony. But get experts in a closed room and opinions can become more divided, or at least more vocal.
Part V: Case Study
EE Times University  
8/23/2013   83 comments
In this final class, we will consider how a modification in the supply chain can change the way an industrial system is designed, deployed, and maintained. Specifically, we will take a look at the industrial embedded computer business of Dell’s OEM division and how a change in infrastructure can impact the whole industry.
Part IV: Getting Lost in the Data
EE Times University  
8/22/2013   120 comments
With so much data becoming available, it can affect the way systems are designed and software is written. In this class we will look at some of the tradeoffs among compressing, encrypting, and transmitting data across a network, particularly in systems where power is a scarce resource.
EDA/IP Weekly Roundup – August 19, 2013
Blog  
8/22/2013   Post a comment
Verific's SystemVerilog parser is added to Stylus compiler; Agilent increases its tie with Gradient; Opera gets multicored, among other tidbits in EDA this week.
IP Roundtable, Part 3: Subsystems & Software
Blog  
8/21/2013   2 comments
Does the integration of larger subsystems make your job easier or more complex? How are people getting on with software integration? Here's what some experts say.
When Statistics Don’t Tell the Whole Truth
Blog  
8/21/2013   8 comments
There are lies, damned lies, and statistics about how fast we're adopting code coverage, functional coverage, and assertions in our everyday work.
Part III: Security
EE Times University  
8/21/2013   113 comments
As sensors become distributed and data is collected from diverse sources, the systems become more vulnerable to attack. What can be done to ensure that both the data and the integrity of the system remain secure from internal and external attacks? In this segment we will look at both hardware and software techniques to secure the system.
Part II: Consolidation
EE Times University  
8/20/2013   125 comments
In this class we will look at what is happening in the compute centers and, in particular, technologies such as multicore and virtualization. Consolidation enables more efficient computing, centralized management, integrated data management, and visualization, as well as enabling new types of applications and automation in industrial systems.


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