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BrianBailey
Member Since: November 26, 2012
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posted in May 2012

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Snapped up before DAC – there will be no Missing Link
News & Analysis  
5/31/2012   1 comment
One of the new exhibitors for DAC this year has been snapped up before the show begins….
EDA/IP Weekly Roundup – May 30th
Blog  
5/30/2012   Post a comment
OCP-IP, Silicon Frontline, Mentor, Tanner, Flexras, DDR, Synopsys, CAST and Xilinx made the lineup today. See here for their news…
Gearing Up for DAC – IP, Flows and Services
Blog  
5/29/2012   Post a comment
This entry is the final entry in the what to see at DAC blog series. It includes listing about the demos that companies will be showing in the areas of IP, Flows and methodologies and services etc...
Catapult + Calypto = ESL power optimization
Blog  
5/29/2012   Post a comment
After one year we see the first results of the transfer of the Catapult technology from Mentor to Calypto. ESL power optimization…
Gearing up for DAC – RTL to GDS II demos
Social Mania  
5/28/2012   Post a comment
This entry is the third in the what to see at DAC blog series. It includes listing about the demos that companies will be showing in the area of RTL to GDS II...
Tektronix believes in embedded instruments
Blog  
5/25/2012   1 comment
On chip instrumentation is becoming a necessity as external observability declines and the uses for the technology grows...
Best of the web – May 25
The Engineering Life - Around the Web  
5/25/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
What were they thinking: Facebook IPO
The Engineering Life - Around the Web  
5/25/2012   5 comments
Facebook didn’t have a great IPO. Was it greed, was it misinformation, was it deceitful…
Power optimization starts early in the process
Blog  
5/24/2012   Post a comment
For many companies, power optimization starts at the RT level, but Docea Power attempts to take it to the ES level…
IP being made more accessible
Product News  
5/24/2012   1 comment
For people who wish to try before buying, the whole notion of reference designs and the implementation of them is a great idea…
High Voltage CMOS process tackles power
News & Analysis  
5/24/2012   Post a comment
The new process provides low specific On-resistance 700V power devices and the lowest mask count in the foundry industry…
EDA/IP Weekly Roundup – May 23rd
Blog  
5/23/2012   Post a comment
Corelis, Space Codesign, OCP-IP, Mentor, NanGate, Tanner, Aldec and Imperas made the lineup today. See here for their news…
Gearing Up for DAC – Above RTL
Social Mania  
5/22/2012   2 comments
This is the second in the series of what to see at DAC blogs. It includes listing about the demos that companies will be showing in the area of design above RTL…
Pulsic to introduce analog and custom digital place and route
Product News  
5/22/2012   Post a comment
Pulsic will introduce a place-and-route implementation solution at DAC this year, including Unity Analog Router, Unity Custom Digital Router, and Unity Custom Digital Placer…
What were they thinking: Chicken Tikka Masala
The Engineering Life - Around the Web  
5/18/2012   4 comments
Who invented Chicken Tikka Masala, and while we are about it, where did the term curry come from...
Gearing Up for DAC – Verification demos
Social Mania  
5/18/2012   2 comments
This entry is the first in the what to see at DAC blogs. It includes listing about the demos that companies will be showing in the area of verification…
Best of the web – May 18
The Engineering Life - Around the Web  
5/18/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
SIG, Panel and more at DAC
Social Mania  
5/17/2012   Post a comment
These are the events that I am involved with at DAC this year. I hope to see you at one of them…
Power Intent Standards
Blog  
5/16/2012   Post a comment
This is an entry in the EDA DesignLine power archive related to power intent standards...
EDA/IP Weekly Roundup – May 16th
Blog  
5/16/2012   Post a comment
Mathworks, MIPS, Imperas, Cadence, Sigrity, Kilopass, EVE, Carbon and ams made the lineup today. See here for their news…
New Companies at DAC: Esencia Technologies
Blog  
5/16/2012   Post a comment
Esencia has just announced the EScala design platform which is primarily aimed at audio and video applications that have compute intensive algorithms...
New companies at DAC for the first time in 2012
Social Mania  
5/15/2012   1 comment
This is the first of a series of blogs preparing you for DAC this year. This one lists the new companies exhibiting for the first time...
Cadence forges closer links between verification components
Product News  
5/15/2012   1 comment
For a long time, it has been said that verification gets no respect. Aspects of this continue to be true, but tool development keeps heading forward…
Tales from the entrepreneurial trenches: Dermott Lynch - Part 2
Engineering Pop Culture!  
5/15/2012   1 comment
This is the first in a new series of articles that talk about the lessons learned by entrepreneurs in the course of their success and failure…
Sigrity tackles chip I/O model extraction problem
Product News  
5/14/2012   Post a comment
Sigrity has introduced XcitePI IO Interconnect Model Extraction. The tool generates chip IO power/ground and signal interconnect models for system-level analysis of high-speed channels and buses...
Best of the web – May 11
The Engineering Life - Around the Web  
5/11/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
What were they thinking: copyrighting APIs
Blog  
5/11/2012   3 comments
In the epic battle between Oracle and Google over the Java API, the jury questions fair use...
EDA/IP Weekly Roundup – May 9th
Blog  
5/9/2012   Post a comment
PLDA, TSMC, CriticalBlue, S2C, Jasper, Tensilica, Synopsys, EVE, Vennsa, Verific, VWorks and Excellicon made the lineup today. See here for their news…
Power 101
Social Mania  
5/8/2012   Post a comment
Introductory series on power in semiconductors...
Enough of the sideshows – it’s time for some real advancement in functional verification!
Blog  
5/8/2012   7 comments
Functional verification has become the congestion point for many designs and the bane of many companies trying to sell their IP...
New Companies exhibiting at DAC: ICScape
Social Mania  
5/7/2012   Post a comment
DAC is quickly approaching and with it we can expect to see many new companies showing their tools for the very first time...
What were they thinking? Stopping a car
Engineering Pop Culture!  
5/4/2012   13 comments
With the power series over, it is time to reinstate some fun. How would you stop a car?
Soft errors can cause headaches at smaller geometries
Product News  
5/2/2012   1 comment
IROC has been in the soft error business for a decade, developing simulation expertise and tools while also providing test and analysis services…
EDA/IP Weekly Roundup – May 2nd
Blog  
5/2/2012   Post a comment
Dialog Semi, Cadence, Atrenta, Austriamicrosystems, eASIC and Arasan made the lineup today. See here for their news…
Apache adds support for 20nm and 3D
Blog  
5/1/2012   Post a comment
Power reduction is the new primary design consideration, and Apache wants to stay ahead of the curve, providing the tools necessary to analyze and optimize it…


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