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BrianBailey
Member Since: November 26, 2012
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posted in June 2013

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IP integration: what standards do we need?
Blog  
6/27/2013   4 comments
IP integration is becoming a very important and difficult issue. What needs to happen to make this easier? Are we developing the right standards?
EDA/IP weekly roundup – June 26th 2013
Blog  
6/26/2013   Post a comment
Accellera, Agilent, Cadence, Gartner, MathWorks, Mentor, Synopsys, Tektronix, UltraSoC, UMC and Verifyter AB made the lineup today. See here for their news…
RoboCup is about to kick off in Eindhoven and Mathworks will be there
Blog  
6/25/2013   1 comment
What has soccer/football got to do with EDA? When it is played by autonomous robots, it is all about design in this student competition…
Semico has some eye popping numbers
Blog  
6/24/2013   Post a comment
Semico Research Corp has been looking into the rising costs associated with new process nodes and the numbers don’t look pretty…
Is small always sexy
Blog  
6/21/2013   1 comment
Silicon Frontline is going for the big devices in its power analysis tool...
What were they thinking: F for parking
Blog  
6/21/2013   5 comments
Parking should not be difficult, unless of course you are misdirected...
DAC Keynote from James Truchard
Blog  
6/19/2013   1 comment
James Truchard says the future is all about platform based design and that if you are an RTL designer, you had better start becoming a software engineer…
EDA/IP weekly roundup – June 19th 2013
Blog  
6/19/2013   Post a comment
Arasan, Cadence, IBM, IEEE, Intellitech, Mentor, Real Intent, Toshiba, UMC and X-FAB made the lineup today. See here for their news…
Atrenta’s Ajoy Bose: lessons from an entrepreneur
Blog  
6/18/2013   1 comment
What would Ajoy Bose say to an aspiring entrepreneur?
Formality tackles ECOs
Product News  
6/18/2013   Post a comment
Synopsys' Formality tackles ECOs and cuts re-verification time from hours to minutes
What were they thinking: A place to sleep
Blog  
6/14/2013   Post a comment
An interesting little patent today that shows how simple a patent can be...
Synopsys releases one library to rule them all
Product News  
6/12/2013   Post a comment
Synopsys has released a new physical library kit and set of scripts that they claim can provide some significant benefits across the entire SoC…
EDA/IP weekly roundup – June 12th 2013
Blog  
6/12/2013   Post a comment
Analog Bits, Atrenta, Carbon, Cypress, Gartner, Imagination, Rambus, SK Hynix, Synopsys, Toshiba and Wi-LAN made the lineup today. See here for their news…
DAC in Austin: success or failure
Blog  
6/11/2013   6 comments
The numbers are in for the 50th anniversary DAC in Austin. How did this year fare compared to previous years…
DAC Keynote: Gregg Lowe
Blog  
6/11/2013   Post a comment
Gregg Lowe of Freescale gave the first of the keynotes at DAC 2013. He says that the Internet of Things will create several challenges such as power efficiency that have to be overcome…
DAC 2013 theme
Blog  
6/7/2013   1 comment
What was the theme for DAC 2013? I think one area became a distinct theme given how broadly it was talked about...
What were they thinking: Slithering a snake
Engineering Pop Culture!  
6/7/2013   6 comments
How many of you have a pet snake and want to take it for slither? Well, you just may need this invention...
EDA/IP weekly roundup of back end and foundry related news – June 5th 2013
Blog  
6/5/2013   Post a comment
ARM, Globalfoundries, Mentor, Samsung and Synopsys made the lineup today. See here for their news…
EDA/IP weekly roundup of product and IP news – June 5th 2013
Blog  
6/5/2013   Post a comment
Adapt-IP, Agilent, Atrenta, ATopTech, Ausdia, Berkeley, Blue Pearl, Cadence, Carbon, CircuitSutra, CMP, Cortus, Forte, IPextreme, Khalifa, Kozio, Mentor, Microsemi, Plunify, Target Compiler, Vayavya and Xilinx made the lineup today. See here for their news…
EDA/IP weekly roundup of standards news – June 5th 2013
Blog  
6/5/2013   Post a comment
Accellera, DAC, IEEE, Stanley Krolikoski, Si2 and TechAmerica made the standards lineup today. See here for their news…
Day one at DAC
Blog  
6/4/2013   Post a comment
Day one of the events at DAC was a busy, busy affair….
ARM announces AMBA 5 CHI - the Coherent Hub Interface
Blog  
6/3/2013   Post a comment
ARM has now named the 16 core architecture with CoreLink cache coherent network and dual memory controllers as AMBA 5 Coherent Hub Interface…
Jasper and Duolog tackle IP integration problems
Blog  
6/3/2013   Post a comment
Jasper and Duolog are creating integrated design and verification flows that tackle some of the toughest problems associated with integrating hundreds of IPs into an SoC…


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