Components
a. Muxes and Demuxes
One of the key building blocks of Sonet transceivers is the multiplexer and demultiplexer. For Sonet OC768 applications, these building blocks need to support broadband data signals up to 50 Gbits/s in order to support FEC (Forward Error Correction) schemes for 40-Gbit/s data transmission.

Using IBM's SiGe 7HP technology, 4:1 multiplexers and 1:4 demultiplexers were designed, fabricated and tested both in on-wafer and package measurements. The multiplexers have been demonstrated to operate up to 70 Gbit/s with the four individual channels being driven by a pattern generator supplying pseudo-random bit sequence at 17.5 Gbits/s with an input clock of 35 GHz. Under nominal operating conditions, 40 to 50 Gbits/s and a power supply of 3.3 V, the chip dissipates 1.5 W. The demutiplexer has also been measured and shown to operate above 56 Gbits/s and has an input sensitivity well below 50 mV. Under nominal operating conditions, 40 to 50 Gbits/s and a supply of 3.3 V, the chip dissipates 1.5 W. The multiplexer and demultiplexer have been designed to operate over a very wide range of data rates, making the chips suitable for test equipment applications as well as for optical link transceivers. In fact, these prototype chips have already been used in commercial test equipment displacing InP-based designs based on performance and power dissipation.

By taking advantage of the integrated passives available with the technology, including varactor diodes and high-Q inductors, it is possible to add phase-locked-loop circuits and build monolithic mux and demux chips containing clock multiplier units and clock and data recovery circuits. Because this is a BiCMOS process, the control loops and state machines, which are required for these chips, can be readily generated using standard CMOS and VHDL design techniques. In fact, many of the closely coupled customized signal-processing and link-monitoring circuits are in CMOS. Today, such levels of integration are achieved only in silicon-based technologies.

Another interesting advance is that of low-voltage bipolar circuit topologies. Although most of the circuits described previously operated in the -3.3- V to -3.6- V range, it is possible to operate low-voltage CML circuits at supplies as low as -1.2 V. A test circuit consisting of a multimodulus divider was demonstrated to readily operate at frequencies up to 9 GHz under a 1.2- V supply. Such low-power circuit techniques can be used to lower the overall power dissipation of a complex, high-speed circuit achieving power levels comparable to that of a CMOS implementation.

b. Laser & EAM Drivers
The breakdown voltage of SiGe 7HP, typically stated as Bvceo where "o" indicates open base, in this case only 1.9 V, is often mistaken as the limit at which transistors can operate without catastrophically failing. Although it is an important figure of merit, it does not represent the practical situation in which a designer uses a transistor. Indeed, in an actual application there is a finite termination with a low- to medium-impedance level placed at the transistor base. Under these conditions, the transistor can readily support a voltage across it of 6 V. Thus, the more interesting metric to consider for these devices is BVcer where "r" represents the termination at the base of the device. Once this consideration is taken, it is clear that SiGe can also be applied to many front-end transceiver applications such as laser diode drivers and electro-absorption modulator (EAM) drivers.

Prototype VCSEL (Vertical Cavity Surface Emitting Laser) circuits have been developed in single driver and array driver formats that are capable of driving VCSELs at data rates of just over 10 Gbits/s while supplying a modulation current of up to 7 mA. A typical power dissipation per channel for the 12-channel VCSEL array driver is only 100 mW, including the VCSEL. A single-channel SiGe VCSEL driver was paired with a VCSEL and next-generation multimode fiber to demonstrate a world record breaking optical link operating at 20 Gbits/s over a 1-km link. A prototype EAM driver has also been demonstrated. This driver is capable of driving over 3.0 V p-p single-ended into a 50-ohm load with a typical power dissipation of 2.5 W at a data rate of 30 Gbits/s. The technology can readily address the receiver side of an optical link being readily suited for transimpedance amplifiers and limiting amplifiers (or post-amplifiers).

c. Post-amplifiers
A key requirement for telecommunication transceivers is limiting amplifiers capable of handling input signals over a very wide dynamic range. A prototype limiting amplifier test circuit targeting 40 Gbits/s has been designed and measured. The circuit is capable of accepting inputs as low as 20 mV and as large as 850 mV p-p single ended and providing an output swing of 450 mV p-p into a 50-ohm load using a -5.2 V power supply. As in the case of the CMU and CDR circuits, CMOS can play a critical role in limiting amplifiers by providing the requisite circuits to perform the feedback control for offset control.

Looking forward to even faster silicon
The next-generation SiGe technology at IBM, SiGe 8HP, will provide transistors with an Ft/Fmax greater than 200 GHz in 0.13-micron lithography. Early test site hardware has already provided record-setting results including ring oscillators exhibiting gate delays of 4.3 ps at 250 to 300 mV p-p swings, beating comparable InP HBT and, at the same time, enabling 55 percent reduction in power dissipation. These transistors will allow designers to readily build full rate OC768 transceivers. An additional benefit will be the dramatic improvement in transceiver power consumption, estimated in the range of 50 percent. Indeed, early test site hardware containing static divider circuits clearly shows that tail currents of less than 1 mA are required to operate the dividers at frequencies of 50 GHz. Design engineers will be able to consider next-generation Ethernet or Sonet transceivers operating at 80 to 100 Gbits/s using half-rate clock architectures. In the wireless regime, frequency bands heretofore unreachable in a silicon technology such as the ISM (Instrumentation, Scientific, Medical) band at 60 GHz can be readily addressed. In a sense, this new silicon technology will enable applications that will often outpace the capability of test equipment engineers.