Noteworthy in the announcement is the fact that this is the first 32-nm, low-power technology that did not have to resort to high-k gate dielectric and metal gates to achieve its performance characteristics, according to TSMC (Hsinchu). In addition, a 0.15-micron² high-density SRAM cell has been realized by 193-nm immersion lithography using double patterning approach, according to the firm.

The company made its announcement through a paper presented at the IEEE International Electron Devices Meeting in Washington, D.C. The paper also revealed that the company had proven the full functionality of the 2-Mbit SRAM test chip with the smallest bit-cell at the 32-nm node.

This leading edge technology is optimized for low power, high density and manufacturing margins with optimal process complexity.

TSMC did not use high-k and metal gates for its own 45-nm process. The company is supposedly working on high-k for the 32-nm node. It's unclear if TSMC will offer high-k -- or not -- for its 32-nm foundry process.