Now, one group thinks they have the answer.

The world's first CMOS circuit using nanotubes as an interconnect was recently designed at Stanford University, in cooperation with Toshiba Corp. I t was fabricated by Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). The 256 ring oscillators on the 11,000- transistor chip ran at 1 GHz, rivaling the speed of other advanced CMOS chips (the iPhone's processor runs at 700 MHz).

"A lot of research labs are working toward using nanotubes to interconnect chips since they have higher electron mobility than copper, and can be grown much smaller. But ours is the first working digital chip to run at commercial speeds of 1 gigahertz," said electrical engineering professor Philip Wong, a professor of electrical engineering at Stanford.

' The chip was designed as a array of ring oscillators with one missing connection. By adding a nanotube to complete the circuit, the chip demonstrated the viability of nanotubes as a substitute for copper wiring. The nanotubes used were multiwalled types measuring five microns in length and from 50 to 100 nanometers in diameter (about the same size as copper wires). Future versions could use single-walled nanotube wires as small as 1 nm in diameter. The chip measured one hundredth of a square inch.

To simplify fabrication and testing of the ring oscillator array, multiplexing circuitry was provided on the chip so that individual ring oscillators could be separately addressed. The nanotubes were placed in the gap to complete the circuit of a ring oscillator using a novel method that floated a solution over the chip suspending thousands of free-floating nanotubes.

Then an alternating current was supplied to the ring oscillators, which attracted the floating nanotubes to precisely the correct gaps in the circuitry. Once a nanotube snapped into place to bridge a particular gap, the AC signal was turned off for that ring oscillator. The solution was then removed and the chip allowed to dry off.

The work was performed with the help of Stanford University electrical engineering doctoral candidate Gael Close, Toshiba engineers Shinichi Yasuda and Shinobu Fujita along with engineeer Bipul Paul of Toshiba America Research (San Jose, Calif.).

The research was funded by Toshiba, the Interconnect Focus Center, Semiconductor Research Corp. and Close's Intel Graduate Fellowship.