As power efficiency technology moves into a new generation, it has become more sophisticated--depending more and more on interaction between ICs. The next generation of power efficiency technology will require a heavy dose of institutional knowledge integration.

A holistic, system-level view of power management and ever-advancing chip technologies is becoming increasingly important, heightening the need for open conversations and collaboration between DSP, SoC, MCU and analog power management designers.

Additionally, semiconductor companies must find ways for system designers to take advantage of the sophisticated techniques built into the chips. Otherwise, all of the potential energy savings cannot be wrung out of a system.

From a system-design perspective components need to work together at a very high level of sophistication, and this begins while the SoC or DSP is still being designed. Analog, MCU and power supply designers can provide invaluable input to the SoC or DSP design team.

As product features grow and consumer expectations rise, the imperative to do more with less never changes. Semiconductor technology is playing a key role in energy conservation by combining efficiency and intelligence. Building efficiency into the chips and system designs that go into products we use daily helps take some of the burden off the consumer.

The migration from 90-nanometer to 65-nm to 45-nm process nodes has produced lower-power chips in large part because higher-density chips run at lower voltages--and power scales as a square of voltage. There are tradeoffs, however, because the thinner isolation layers of advanced processes allow greater leakage current when a particular circuit is quiescent.

To control power loss from active currents during the periods when a DSP, applications processor or system-on-chip (SoC) is not adding functional value, IC designers have invented techniques such as clock gating, which turns off selected parts of the chip when they are not being used.

More dramatic results can be achieved by turning the entire chip off when it is not being used by the system. While effective, this technique sometimes calls for the intervention of an extremely low-power MCU. This also requires very tight MCU-SoC linkage, because when the system calls for the larger chip to be turned on, it must happen instantaneously and the SoC must also wake up quickly.

Although these techniques continue to be very valuable, more nuanced approaches can add to power savings.

Texas Instruments' Smart Reflex technology, for example, takes advantage of variations over process corners and monitors a device's activity, operating mode and temperatures at silicon junctions. This data allows system designers to optimize power efficiency by dynamically adjusting voltage and frequency. Smart Reflex technology can also coordinate power usage in multicore chips to cut down on chip-level power.